We are looking for an experienced Analog Layout Engineer eager to make an impact by designing high-quality analog layouts across various technology nodes.

QUALIFICATIONS AND SKILLS

• Master’s degree in Electronics or Electrical Engineering (or equivalent experience).
• Strong expertise in designing various analog blocks, integrating them at the top level, and performing signoff checks.
• Proficiency in EDA tools for design, verification, and layout implementation.
• In-depth understanding of Layout Dependent Effects (LDE) in deep submicron technology nodes.
• Hands-on tape-out experience across multiple technology nodes.
• Familiarity with Radiation Hardening techniques and their implementation in layouts (a plus).
• Experience with version control tools such as SVN, Cliosoft, or similar.
• Excellent communication skills in English (both written and verbal).

• Design analog layouts for circuits such as PLL, BG, LVDS, and IVREF for space applications and cutting-edge research projects.
• Perform physical verification (DRC, LVS, EM/IR) and other essential checks to ensure design integrity.
• Execute floor planning and top-level routing, considering multiple power domains and mixed-signal design challenges.
• Conduct chip-level validation, including dummy fill and sign-off checks, ensuring smooth tape-out.
• Deliver high-quality results on time, meeting project deadlines.
• Archive reports and checklists for efficient project documentation.
  Location: Leuven, Belgium