Staff, STA (Static Timing Analysis) Engineer at Tenstorrent

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

18 Dec, 25

Salary

0.0

Posted On

19 Sep, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, RISC-V, Tcl, Perl, Python, Timing Closure, Physical Design, RTL, Verification, Timing Reports, Timing Constraints, CDC Analysis, Low-Power Techniques, MMMC Flows, ECO Handling, Debugging

Industry

Computer Hardware Manufacturing

Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. In this role, you’ll lead timing closure efforts across block and full-chip levels, working closely with physical design, RTL, and verification teams across multiple technology nodes, including 5nm and 3nm. This role is onsite, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Have hands-on experience in STA for complex SoCs, from block to full-chip level. Comfortable using tools like PrimeTime, Tempus, or PTPX. Strong in scripting with Tcl, Perl, or Python to automate workflows. Confident working cross-functionally to solve timing challenges and drive closure. What We Need Ability to define and drive STA methodology across different corners and modes. Skill in analyzing timing reports and working across teams to fix violations. Experience with timing constraints, CDC analysis, and low-power techniques. Familiarity with MMMC flows, ECO handling, and debugging timing exceptions. What You Will Learn The art of navigating timing closure on advanced nodes like 5nm and 3nm. How to collaborate across global teams to deliver high-performance silicon. Best practice in improving STA signoff processes and checklists in a fast-paced environment. Ways to sharpen your debugging skills with real silicon use cases and first-silicon success targets. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Responsibilities

Lead timing closure efforts across block and full-chip levels for AI and RISC-V SoCs. Collaborate with physical design, RTL, and verification teams to ensure first-pass silicon success.