Analog Design Engineer

at  Intel

JOB DESCRIPTION

We are looking for a highly motivated analog design engineer to join the IP, Security and Client Product Group (ISCP) Circuits team for Intel’s next generation of chipsets/SOC.
As part of the team, you will be working across different teams within the organization: architecture, technology development, IP designers, package and platform engineers to design and integrate best in class Hard IPs.

Responsibilities for this role include, but are not limited to:

• Design, simulation, characterization, and integration of on-die power delivery circuits such as: LDOs, power gates, voltage monitors.
• Work with architecture team to define and deliver the next generation of Hard IPs for future SOCs.
• Design, simulation, characterization and integration of circuits and components such as PLLs, DLLs, system monitors: thermals, voltage, clock.

Behavioral traits:

• Willing to work effectively both independently and as a team.
• Technical leadership with good communication skills.
• Advanced interpersonal and problem-solving skills.
• Willing to work across the organization to achieve goals and thrive in a team-orientated environment.

QUALIFICATIONS

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your
schoolwork/classes/research and/or relevant previous job and/or internship experiences.

MINIMUM QUALIFICATIONS

The candidate must have a bachelor’s degree in electrical/computer engineering or related field and 3+ years; OR master’s degree in electrical/computer engineering or related field and 2+ years of experience in:

• Analog circuits design.
• Solid foundation knowledge of SOC design, timing analysis and reliability analysis.
• Advanced English level.

PREFERRED QUALIFICATIONS

• PhD in Electrical/Computer Engineering or related field.
• 2+ years of experience working with mixed signal design and post-silicon debug.

• Design, simulation, characterization, and integration of on-die power delivery circuits such as: LDOs, power gates, voltage monitors.
• Work with architecture team to define and deliver the next generation of Hard IPs for future SOCs.
• Design, simulation, characterization and integration of circuits and components such as PLLs, DLLs, system monitors: thermals, voltage, clock