2025 Fall Intern, CPU Performance Architect at Samsung Research America Internship
Mountain View, California, USA -
Full Time


Start Date

Immediate

Expiry Date

16 Sep, 25

Salary

63.0

Posted On

17 Jun, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Computer Architecture, Design Principles, Collaborative Environment, Compilers, Programming Languages, Computer Engineering, Microarchitecture, X86

Industry

Information Technology/IT

Description

Lab Summary: The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.
Position Summary: We are seeking a highly motivated intern to join our CPU Architecture team in Fall 2025. As an intern, you will have the opportunity to work alongside experienced engineers to contribute to the design, development, and modeling cutting edge CPU microarchitectures and its subsystem. You will assist in the design and implementation of key components of modern processors, including pipeline stages, memory hierarchy, and communication protocols, gaining hands-on experience in cutting-edge CPU technologies.

REQUIRED SKILLS:

  • Currently pursuing a Master’s or PhD degree in Electrical Engineering, Computer Engineering, or related fields
  • Strong understanding of CPU architectures, instruction sets (such as x86, ARM, RISC-V), and microarchitecture design principles (out-of-order execution, multi-level caches, branch prediction, data prefetching etc.)
  • Experience in microarchitecture modeling, simulation, and performance evaluation
  • Excellent problem-solving skills and the ability to work in a fast-paced, collaborative environment
  • Coursework or experience in computer architecture, compilers, microprocessor design, parallel programming, digital logic design etc.
  • Proficient in C/C++ and Python programming languages
  • Experience creating or integrating simulation models of multi-core SoC subsystems at different levels of abstraction (e.g., cycle-accurate and TLM)

How To Apply:

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Responsibilities
  • Assist in the design and development of CPU microarchitecture components such as pipelines, execution units, and caches
  • Perform performance modeling and analysis of hardware features, applications, benchmarks, and uses cases
  • Collaborate with senior engineers on micro-architectural modeling and analysis to improve performance, power, and area efficiency
  • Participate in architecture definition discussions and assist in performance analysis using simulators and tools
  • Debug and resolve design issues using simulation and hardware emulation environments
  • Document design work, test plans, and test cases as part of the project deliverables
  • Leverage Industry standard tools and/or create in house tools to speed up performance evaluation and analysis
  • Complete other responsibilities as assigned
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