AI Accelerator Compiler & Framework Researcher at Huawei Technologies Co. Ltd - Singapore

Crissier, Vaud, Switzerland -

Full Time

Start Date

Immediate

Expiry Date

26 Jan, 26

Salary

0.0

Posted On

28 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Compiler Frameworks, NPU Architectures, Python, C/C++, AI Frameworks, Model Optimization, xPU Toolchains, DSP Toolchains, System Software, High-Level Models, Automated Model Conversion, Quantization, Adaptive Deployment, Memory Allocation, Parallel Execution, Documentation

Industry

Telecommunications

Description

About Huawei: Huawei is a leading global ICT (information and communications technology) solutions provider. We’re driven by innovation, open collaboration, and strong operations. Our ICT solutions, products, and services are used in over 170 countries and regions, serving more than one-third of the world’s population. With 180,000 employees, Huawei is committed to enabling the future information society and building a Better Connected World. Huawei’s Research Centre in Lausanne focuses on advanced technical research, architecture evolution design, and strategic technical planning in computer architecture. We are currently looking for Researchers for our new Computer Architecture Innovation Lab. What You’ll Do: NPU-Centric Python Framework Design: Design smart cross-layer optimizations for compilers, runtimes, and frameworks (e.g., PyTorch, vLLM) to boost NPU efficiency. Work on automated model conversion, quantization, and adaptive deployment for NPU workloads. Compiler & Toolchain Innovation: Build and improve NPU-specific compiler stacks (LLVM/TVM/GCC) to turn high-level models into super-fast NPU instructions. Optimize scheduling, memory allocation, and parallel execution strategies. Hardware-Software Co-Design: Work closely with hardware teams to define NPU ISA extensions, microarchitecture features, and performance counters for maximum efficiency. Research & Ecosystem Leadership: Publish your work in top conferences (ISCA, ASPLOS, MLSys) and contribute to open-source projects. Help developers use NPU frameworks through tools, documentation, and partnerships. Who We’re Looking For: Master’s degree + 3 years of system software experience or fresh PhD graduates in Computer Science, Computer Engineering, or related fields. Strong knowledge of compiler frameworks (LLVM, GCC, TVM, XLA) and NPU/GPU architectures. Proficiency in Python and C/C++ for system-level programming. Familiarity with AI frameworks (PyTorch, TensorFlow) and model optimization is a plus. Experience with xPU/DSP toolchains is a plus. Excellent English communication skills.

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Responsibilities

Design smart cross-layer optimizations for compilers and frameworks to enhance NPU efficiency. Collaborate with hardware teams to define NPU ISA extensions and improve compiler stacks.