AI/ML ASIC Architect at Sandisk

Milpitas, California, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Aug, 26

Salary

322092.0

Posted On

22 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Architecture, PCIe, UCIe, CXL, DMA Engines, LLM Workload Analysis, HBM, NoC, GPU Architecture, CUDA Programming, NAND Flash, ARM Processors, AXI Interconnects, PPA Analysis, Microarchitecture, Hardware-Software Co-optimization

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description In this AI/ML ASIC Architecture position, you will develop AI Storage Solutions based advanced system architectures and AI/ML Accelerator ASIC architecture specifications for Sandisk’s next generation products. You will drive, initiate, and analyze frontend architecture of the AI/ML Accelerator product. As an AI/ML ASIC Architect you will help drive new architecture initiatives that leverage the state-of-the-art frontend interfaces like UCIe, PCIe, CXL, etc that integrates AI Storage Solutions with xPU in a 3D package system. You will drive the AI Storage Solutions based architecture. You will exercise your technical expertise and excellent communication skills to collaborate with design and product planning with an eye towards delivering innovative and highly competitive adaptive accelerators solutions. Typical activities include writing architecture spec, working with other architects in the team, work with RTL/DV/Simulation/Emulation/FW teams to evaluate these changes and assess the performance, power, area, and endurance of the product. You will work closely with excellent colleague engineers, cope with complex challenges, innovate, and develop products that will change the data centric architecture paradigm. Essential Duties and Responsibilities: Responsible for driving the AI/ML ASIC architecture that integrates the AI Storage with GPU/TPU/xPU accelerators, with a particular focus on I/O subsystems connected over UCIe/ PCIe/CXL Author architecture specifications in clear and concise language for AI/ML xPU based Accelerator using AI Storage Solutions. Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric. Create flexible and modular I/O subsystem architectures that can be deployed in either Chiplet, monolithic or 3D form factors. Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets. Define SoC subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs. Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase. Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap. Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase. LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products. Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth Architect memory-efficient inference/training systems utilizing techniques like pruning, quantization with MX format , continuous batching/chunked prefill, and speculative decoding Collaborate with internal and external stakeholders/ML researchers to disseminate results and iterate at rapid pace Qualifications Required: Bachelors or Masters or PhD in Computer/Electrical Engineering with 15+ years of hands-on Architecture experience authoring specifications Strong technical background architecting ASIC, SoC, or I/O subsystems involving PCIe/UCIe/CXL and DMA engines Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU Good understanding of computer/graphics architecture, ML, LLM Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech) KV cache optimization, Flash Attention, Mixture of Experts Deep experience optimizing large-scale ML systems, GPU architectures Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering Knowledge of ARM Processors and AXI Interconnects Preferred: Familiarity and background in UCIe, CXL, NVLink, or UAL microarchitecture and protocols is a plus Familiarity with High-speed networking: InfiniBand, RDMA, NVLink is a plus Expert knowledge of transformer architectures, attention mechanisms, and model parallelism techniques Multi-disciplinary experience, including familiarity with Firmware and ASIC design Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations Proven track record architecting distributed training systems handling large scale systems Previous experience with NVMe storage systems, protocols, and NAND flash – advantage Additional Information Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 05/25/2026 (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. #LI-KH1 Compensation & Benefits Details An employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future. You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards. We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan. Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company’s sole discretion, consistent with the law. Salary Range: 194,425.00-322,092.00 Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Milpitas Office--LOC_WDT_USCA25

Responsibilities

Develop AI/ML Accelerator ASIC architecture specifications and drive the frontend architecture for next-generation AI Storage Solutions. Collaborate with cross-functional teams to define I/O subsystems and optimize performance, power, and area (PPA) for large-scale ML systems.