AMTS Verification Engineering at Rambus

, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 Jul, 26

Salary

0.0

Posted On

26 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Verilog, UVM, DDR Verification, Testbench Architecture, Debugging, I2C, I3C, DDR3, DDR4, DDR5, Memory Protocol, Verification Sign-off, Test Planning, IP Verification, Sub-system Verification

Industry

Semiconductor Manufacturing

Description

Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional AMTS Verification Engineer to join our Memory Interface chips team in Bangalore . In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. As a AMTS Engineer, you’ll play a pivotal role in (DDR Verification, starting from understanding the design till Verification sign-off, and also to support the Validation team post-tapeouts ). In this full time role, you’ll report directly to our Director. Our MIC team is dedicated to produce high speed DDR products at a high quality to meet the industry requirements, and your contributions will be instrumental in closing the Verification requirements of these products. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the product requirements from the specifications and beyond Planning and execution to meet the verification sign-off criteria Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system using UVM methodology Guide and mentor the team to meet the sign-off requirements Work with architects, designers and post-silicon teams Qualifications Bachelor's or Master's degree in Electronics with 2+ years of relevant experience Expertise in System verilog and UVM Strong debugging skills Experience in all verification aspects from understanding the design requirements till sign-off Should have created Testbench architectures, as well as build verification setup from scratch to ensuring successful verification closure of reasonably complex designs Ability to communicate technical and project issues to business and technical senior management. Must have very good verbal and written communication skills Experience in I2C/I3C Protocol & DDR3/4/5 memory protocol knowledge (preferrable) With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.

Responsibilities

The AMTS Verification Engineer will plan and execute verification sign-off for complex memory interface chips using UVM methodology. They will also develop test plans and infrastructure while mentoring the team and collaborating with architects and post-silicon teams.