Analog Layout Engineer at Apple

Cambridge, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

18 Aug, 26

Salary

0.0

Posted On

20 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Layout Design, Mixed-Signal Layout, FinFET Technology, SKILL, Perl, TCL, Shell, Python, Cadence Virtuoso, Cadence Innovus, Physical Verification, Floor-planning, DFM, PCell Creation, Machine Learning, AI Concepts

Industry

Computers and Electronics Manufacturing

Description

We live in a mobile and device-driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that dedication. The success we are tackling will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk. Join Apple's Silicon Engineering Group (SEG) and be at the forefront of crafting the next generation of Apple's systems-on-chip (SOCs). Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Senior Analog Layout Engineer to chip in to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. DESCRIPTION As a Senior Layout Engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging sophisticated tools. Your work will involve crafting custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. MINIMUM QUALIFICATIONS Extensive years of experience in analog/mixed-signal layout design, with expertise in deep submicron CMOS circuits and extensive years in FinFET technologies experience. Proficiency in SKILL, Perl, TCL, Shell, and/or Python Programming/scripting. Familiar with Machine Learning and AI concepts. Track record in implementing analog layout designs, achieving optimal performance (eg. Matching, low noise, and low power consumption. Must recognise failure-prone circuit and layout structures, have experience with analog and DFM best practices, and be able to identify the best approach to solving problems. High proficiency in custom and standard cell-based floor-planning and hierarchical layout assembly. Technical understanding of IR drop, RC delay, electromigration, self-heating, and coupling capacitance. High proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.) Experience using Cadence Virtuoso's advanced features (XL, EAD, APR, and Constraint Manager) Excellent communication skills and ability to collaborate effectively with multi-functional teams. Additional skill: Cadence Innovus CAD Automation experience PCell creation experience PREFERRED QUALIFICATIONS B.S. EE & CS or equivalent, Excellent knowledge of Mixed-Signal and RF Integrated Circuits is helpful MSEE or Ph.D. in Electrical and Computer Engineering preferred Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants

Responsibilities

Translate design concepts into silicon by crafting custom analog designs for SOCs, including SerDes, PLLs, and sensors. Collaborate with circuit designers and multidisciplinary teams to optimize performance for Apple products.