As a member of the RL subsystem architecture team you will play a key role in performance architecture and modeling. You will analyze our key workloads (graphics rendering, display, audio, computer vision, or color imaging) and collaborate with IP architects and execution engineers to architect subsystems that are SW usable, performant and power efficient. You will also act as a key point-of-contact representing the team with varying internal and external partners, in a highly cross-functional environment, delivering on proof of concepts for workloads and other significant demands.

MINIMUM QUALIFICATIONS:

• 2+ years of performance modeling experience with programming (C/C++ or SystemC-TLM) and scripting (Python)
• 1+ years of experience evaluating architectural trade-offs in performance key performance metrics
• 1+ years of expertise with post-silicon to pre-silicon correlation analysis
• 1+ years of experience with System on Chip (SoC) Architecture, NoCs, memory subsystems, and heterogeneous compute principles

PREFERRED QUALIFICATIONS:

• 2+ years of experience with bare-metal programming, micro-benchmarking, etc
• Exposure to power concepts and low power design principles
• Familiarity with developing and utilizing telemetry solutions to analyze and profile workloads

• Own performance models for system interconnect, cache, memory hierarchy analysis
• Own Subsystem Network on Chip (NoC) architecture specification, design and characterization
• Lead Intellectual Property (IP) performance bottleneck analysis using traffic traces from pre/post silicon platforms
• Lead analysis and configuration of subsystem caches for optimal performance
• Drive IP latency hiding features and Quality of Service (QoS) recommendations for each compute engine
• Collaborate with various partners to deliver documentation and proof of concepts for workloads running on these subsystems