WHAT YOU WILL DO Own the architecture, implementation and integration of the antenna controller FPGA, from requirements through to verified hardware.
Support the design and verification of ASIC cores.
Write clean, modular and maintainable RTL that meets functional, timing and resource requirements.
Define and implement interfaces between the processor subsystem, FPGA and beamforming chips, including register maps, control sequencing and status reporting.
Develop self-checking testbenches, simulations and automated regression tests to verify RTL blocks and integrated designs.
Manage FPGA synthesis, implementation, timing constraints and timing closure, with sound clock and reset-domain crossing practices.
Work with software, hardware and systems engineers to resolve interface requirements, review designs and make practical implementation trade-offs.
Create and maintain design documentation, interface specifications, verification plans and test results.
Support hardware bring-up, lab-based verification and system integration, identifying the causes of faults and resolving them in line with project priorities.
WHAT YOU WILL BRING Significant FPGA development experience, including delivery of complex designs using Xilinx or Intel devices and their associated toolchains.
Strong proficiency in VHDL, Verilog or SystemVerilog, with a disciplined approach to readable, reusable and synthesizable RTL.
Practical experience developing self-checking testbenches, running simulations and debugging RTL.
A sound understanding of timing constraints, timing closure, reset design and safe clock-domain crossings in multi-clock systems.
Experience designing processor-to-FPGA interfaces and implementing control protocols such as SPI, I2C and UART.
Confidence bringing up and debugging hardware in the lab using embedded logic analysers, oscilloscopes and other test equipment.
Familiarity with Linux, version control and scripting to automate builds, tests and development workflows.
Strong technical judgement, clear written and verbal communication, and the ability to take ownership while working across engineering disciplines.
A bachelor’s degree in Electrical or Computer Engineering, or equivalent industry experience and professional training.
PREFERRED EXPERIENCE The following experience would be valuable: ASIC RTL design or verification, including familiarity with synthesis flows or structured verification methods such as UVM.
SoC platforms such as Zynq, and embedded software development in C or C++.
Python, Bash or Tcl scripting, and continuous integration using tools such as Jenkins or GitLab CI/CD.
High-speed communications interfaces, fixed-point signal processing, phased arrays or wireless communication systems.
Responsibilities
WHAT YOU WILL DO Own the architecture, implementation and integration of the antenna controller FPGA, from requirements through to verified hardware.
Support the design and verification of ASIC cores.
Write clean, modular and maintainable RTL that meets functional, timing and resource requirements.
Define and implement interfaces between the processor subsystem, FPGA and beamforming chips, including register maps, control sequencing and status reporting.
Develop self-checking testbenches, simulations and automated regression tests to verify RTL blocks and integrated designs.
Manage FPGA synthesis, implementation, timing constraints and timing closure, with sound clock and reset-domain crossing practices.
Work with software, hardware and systems engineers to resolve interface requirements, review designs and make practical implementation trade-offs.
Create and maintain design documentation, interface specifications, verification plans and test results.
Support hardware bring-up, lab-based verification and system integration, identifying the causes of faults and resolving them in line with project priorities.
WHAT YOU WILL BRING Significant FPGA development experience, including delivery of complex designs using Xilinx or Intel devices and their associated toolchains.
Strong proficiency in VHDL, Verilog or SystemVerilog, with a disciplined approach to readable, reusable and synthesizable RTL.
Practical experience developing self-checking testbenches, running simulations and debugging RTL.
A sound understanding of timing constraints, timing closure, reset design and safe clock-domain crossings in multi-clock systems.
Experience designing processor-to-FPGA interfaces and implementing control protocols such as SPI, I2C and UART.
Confidence bringing up and debugging hardware in the lab using embedded logic analysers, oscilloscopes and other test equipment.
Familiarity with Linux, version control and scripting to automate builds, tests and development workflows.
Strong technical judgement, clear written and verbal communication, and the ability to take ownership while working across engineering disciplines.
A bachelor’s degree in Electrical or Computer Engineering, or equivalent industry experience and professional training.
PREFERRED EXPERIENCE The following experience would be valuable: ASIC RTL design or verification, including familiarity with synthesis flows or structured verification methods such as UVM.
SoC platforms such as Zynq, and embedded software development in C or C++.
Python, Bash or Tcl scripting, and continuous integration using tools such as Jenkins or GitLab CI/CD.
High-speed communications interfaces, fixed-point signal processing, phased arrays or wireless communication systems.
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