ASIC Digital Design Engineer at Avicena Tech

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

02 Jan, 26

Salary

0.0

Posted On

04 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Verilog, SystemVerilog, Design Verification, Logic Synthesis, Timing Closure, DFT Insertion, Linting, CDC Analysis, Documentation, Collaboration, Scripting, EDA Tools, Timing Constraints, Low-Power Design, High-Speed Digital Design

Industry

Description

About the role: Avicena is seeking a skilled and enthusiastic ASIC Digital Design Engineer to join our innovative team. You'll be instrumental in developing high-speed, low-power digital integrated circuits (ICs) for our next-generation photonics and optical interconnect solutions. This role offers the chance to work on the cutting edge of silicon photonics, driving the future of data communication. Responsibilities: RTL Design and Coding: Develop and implement high-quality, efficient Register Transfer Level (RTL) code using Verilog or SystemVerilog for complex digital modules, ensuring compliance with architectural specifications. Design Verification: Collaborate closely with the verification team to define test plans, review coverage, and debug functional and timing issues using simulation tools. Synthesis and Timing Closure: Perform logic synthesis and work on timing constraints, static timing analysis (STA), and timing closure to meet frequency goals, power targets, and area requirements. DFT Insertion: Incorporate Design-for-Test (DFT) structures, including SCAN and BIST, to ensure testability and high-quality manufacturing. Linting and CDC: Perform extensive linting checks and Clock/Reset Domain Crossing (CDC/RDC) analysis to ensure robust, clean, and reliable RTL code. Documentation: Generate clear, detailed technical documentation for design specifications, implementation details, and verification results. Collaboration: Interface with architecture, verification, physical design (backend), and silicon validation teams to ensure seamless integration and successful tape-out. Qualifications: Required: Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5+ years of industry experience in frontend digital IC design. Expertise in HDLs: Strong proficiency in Verilog or SystemVerilog for complex ASIC/SoC design. ASIC Flow Knowledge: Solid understanding of the complete ASIC design flow from specification to tape-out. Tool Experience: Hands-on experience with industry-standard EDA tools for simulation, synthesis (e.g., Cadence Genus, Synopsys Design Compiler), STA (e.g., Cadence Tempus, Synopsys PrimeTime), linting, and formal verification. Timing and Constraints: In-depth knowledge of timing constraints (SDC) and experience achieving timing closure in advanced technology nodes. Scripting: Proficiency in scripting languages such as Tcl or Python for design automation. Preferred (Nice to Have): Experience with high-speed digital design, SerDes, or optical interconnects. Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques. Familiarity with low-power design techniques and methodologies. Experience with UVM-based verification environments. Knowledge of photonics or mixed-signal IC design concepts.

Responsibilities

Develop and implement high-quality RTL code for complex digital modules and collaborate with the verification team to define test plans and debug issues. Ensure seamless integration with architecture, physical design, and silicon validation teams for successful tape-out.