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ASIC Digital Design Engineering Intern at Synopsys
Mississauga, ON, Canada -
Full Time

Start Date

Immediate

Expiry Date

16 Oct, 25

Salary

0.0

Posted On

17 Jul, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Good communication skills

Industry

Information Technology/IT

Description
Responsibilities
  • Developing RTL code, modeling analog blocks, and writing comprehensive testbenches in SystemVerilog.
  • Defining synthesis design constraints and resolving static timing analysis (STA) issues to ensure robust chip performance.
  • Establishing Clock/Reset domain crossing design constraints for reliable integration.
  • Debugging RTL and gate-level simulation failures to drive design quality and innovation.
  • Collaborating with experienced engineers and cross-functional teams to solve complex digital design challenges.