CATEGORY ENGINEERING HIRE TYPE EMPLOYEE JOB ID 10280 REMOTE ELIGIBLE NO DATE POSTED 17/07/2025

The work location for this position is Ottawa. The hiring manger may be open to consider candidates willing to work out of Toronto (Mississauga) location.

• Architecting, developing, and delivering RTL designs for High Bandwidth Memory PHY IP, leveraging SystemVerilog and Verilog.
• Collaborating closely with analog and mixed signal design teams to ensure seamless integration and optimal performance.
• Translating architecture and industry-standard specifications into clear, implementable RTL and technical documentation.
• Automating design flows and verification processes using scripting languages to enhance productivity and streamline development.
• Debugging complex hardware issues at both the RTL and system levels, including physically aware synthesis and timing closure.
• Participating in and guiding the full ASIC and IP development lifecycle, including DFT/DFM flows and design reviews.
• Mentoring junior engineers and fostering knowledge-sharing across global teams.