WE ARE:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

YOU ARE:

We are seeking a highly motivated and innovative digital design engineer with a solid knowledge of ASIC development flow. As an ideal candidate, you are passionate about technology and thrive in a dynamic environment. You have a strong theoretical and practical background in high-speed serializer and data recovery circuits, and you are eager to contribute to the development of the next generation of NRZ and PAM-based SerDes products. You possess excellent communication skills and can effectively interact with different design groups and customer support teams. Your self-motivation and proactive approach enable you to meet tight deadlines while maintaining high design quality. You exhibit the ability to produce excellent results both independently and as part of a team. Your experience in RTL coding, synthesis design constraints, and resolving STA issues makes you a valuable asset to our team. If you are ready to take on new challenges and work with a veteran team of digital and mixed-signal engineers, we want to meet you.

• Designing and verifying complex digital blocks for high-speed SerDes products.
• Writing block-level test-cases, including constrained directed random tests.
• Collaborating with mixed-signal design and verification teams to develop high-end mixed-signal designs.
• Developing and maintaining RTL code, modeling analog blocks, and writing complex system-level test-benches in Verilog.
• Defining synthesis design constraints and resolving STA issues and gate-level simulation failures.
• Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams.