ASIC Digital Design, Staff Engineer at Synopsys
București, , Romania -
Full Time


Start Date

Immediate

Expiry Date

05 Sep, 25

Salary

0.0

Posted On

05 Jun, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Systemverilog

Industry

Information Technology/IT

Description

CATEGORY ENGINEERING HIRE TYPE EMPLOYEE JOB ID 10023 REMOTE ELIGIBLE NO DATE POSTED 09/03/2025

Synopsys, a world leader in the Semiconductor IP industry, is seeking an ASIC Digital Verification Engineer whose mandate is to:

  • Work in a Digital Design and Verification Development team contributing to the development and validation of complex digital circuitry for high-speed interface IP.

  • Conceptualize,

    design, integrate, validate and verify Test Environment components, sequences, checkers and coverage, according to the mandates on the Verification Plan, Team Methodology, and Group goals and objectives.

  • Debug failures from Test Environment down to RTL i

mplementation,

search and determine root causes, suggest and implement fixes and/or workarounds, document and track.

  • Collaborate with peers and superiors to help shape and improve the Test Environment, to achieve best quality and results. Guide junior team members to meet both their and the overall objectives.
  • Analyze metrics, provide feedback and plan of action, and f

ollow-through.

  • Build productive working

relationships,

not only within the team but across teams and business groups.

  • Participate in applicable

product/projec

t reviews.

  • Prepare and present reports of Test Plan coverage, Quality of Results, Performance results, etc.

Key Qualifications

  • University degree in Electronics Engineering or Computer Science
  • Deep Knowledge of IC/Digital Design and Verification flows
  • Comprehensive knowledge of SystemVerilog and UVM
  • Comprehensive experience with Simulation tools
  • Very good

problem-solvin
g skills, capable of considering and describing multiple
scenarios/appr

oaches

  • Good team-player
  • Good organizational skills
  • Good English skills, both verbal and written

Preferred Experience

  • 5+ years of relevant experience is highly preferred
  • Experience in S

ystemVerilog/U

VM

  • Proficiency in at least one

object-oriente

d programming language

  • Exposure to Unix, Python, Perl and TCL scripting
  • Experience with collaboration tools such as
Responsibilities

Please refer the Job description for details

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