* Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog, following established coding standards and quality checks

* Participate in architecture exploration and contribute to design specifications that guide both implementation and verification

* Run synthesis exploration and constraints mapping, analyze timing and power results, and iterate on your RTL to meet performance targets

* Support DFT and ATPG flows and coverage analysis

* Generate high quality documents targeting different audiences: customer consumable and to support design implementation and verification teams.

* Collaborate with verification engineers to define testbenches, debug failures, and close coverage gaps

* Continuous integrate AI-assisted tools into your workflow to improve coding efficiency, debugging speed, and code review quality

The Impact You Will Have

* Your RTL will ship as part of Synopsys IP that powers semiconductor designs across automotive, mobile, data center, high performance computing and AI applications

* The quality and clarity of your design documentation will directly reduce integration time for customers and internal teams

* Your synthesis and timing work will determine whether IP blocks meet performance and power targets that define product competitiveness

* The DFT structures you design will enable high test coverage and reduce manufacturing defects in silicon

* Your collaboration with verification teams will help to anticipate issue detection, reducing costly respins and schedule delays

* The design patterns and flows you establish will influence how the broader mixed signal IP team approaches future projects

* Your adoption of AI tools will help the team move faster and set new standards for productivity across the Porto site

What You'll Need

* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field

* At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows

* Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL) for RTL design and behavioral modeling.

* Solid understanding of DFT and ATPG methodologies

* Experience with synthesis flow, constraints mapping, timing analysis, and power optimization in a production design environment

* Fluency in English, both written and spoken, for documentation and cross-site collaboration

* Experience with high-speed memory interfaces such as DDR/HBM is a strong plus