YOU ARE:

We are seeking a highly motivated and innovative Sr Staff digital verification engineer. The ideal candidate is passionate about technology, driven by challenges, and eager to work on cutting-edge SerDes products. You bring a wealth of experience in digital verification, and you are proficient in SystemVerilog/UVM. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to guide junior peers and network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams. You are self-motivated, proactive, and committed to producing high-quality designs while meeting tight deadlines.

• Verifying ASIC RTL designs at both chip and block levels
• Defining and tracking verification testplans
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing SystemVerilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis
• Guiding junior peers and networking with senior personnel within and outside the functional area