Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.

MINIMUM QUALIFICATIONS:

• 2+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
• RTL development using Verilog, System Verilog and HLS

PREFERRED QUALIFICATIONS:

• Experience in CPU, NOC, Memory and Peripheral Subsystems
• Experience with Synthesis, Timing Closure and Formal Verification Methodology
• Experience in data path development

• Architecture exploration
• Micro-architecture development
• Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power