ASIC Engineer, Design Verification at Meta

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

26 Apr, 26

Salary

0.0

Posted On

26 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design Verification, UVM, Verilog, SystemVerilog, C/C++, Python, Simulation, Debugging, Collaboration, Networking, Data Center Applications, Performance Verification, Test Planning, Emulation, Mentoring, Continuous Improvement

Industry

Software Development

Description

Meta is hiring Application-Specific Integrated Circuit (ASIC) Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of a team working with the best in the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Lead verification of multiple complex sub-systems or SoC from concept to Silicon. Develop test plans for SoC/Chiplet interoperability, usecase and performance verification. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Perform and guide teams in simulation-based testing, including functional, performance, and compliance testing . Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality Stay up-to-date with industry trends, standards, and best practices related to Compute, High-Speed Interconnects, Networking. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry. Mentor other engineers to drive and deliver high confidence verification for highly complex ASIC projects Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience At least 12+ years of relevant experience Track record of 'first-pass success' in ASIC development cycles Hands-on experience in Verilog, SystemVerilog, UVM , C/C++, Python based verification Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in one or more of the following areas along with functional verification - SIMT, PCIe, HBM, Ethernet, 400G MAC, NIC, RDMA, TSO, LRO, PSP, RoCE (RDMA over converged Ethernet), Congestion Control etc Experience with Design verification of Data-center applications like AI/ML, Networking, GPU and Video designs Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred Qualifications 20+ years of hands-on experience in development of UVM based verification environments from scratch Experience in technically planning, executing and leading the verification of multiple complex Sub-Systems or SoC or from multi-chiplet Solutions from Architecture to Silicon Expertise in the Networking domain with in-depth experience working with AI Compute, High-Speed IO Interconnects, Die-to-Die Interconnects, Ethernet, 400G MAC, RDMA, RoCE, NIC, TSO, LRO, TimeSync protocols Experience with IP or integration verification of high-speed interfaces like Ethernet, PCIe, DDR, HBM Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with simulators and waveform debugging tools Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation Experience working across and building relationships with cross-functional design, model and emulation teams

Responsibilities

The Design Verification Engineer will define and implement verification plans, build test benches, and lead the verification of complex sub-systems or SoCs. They will collaborate with cross-functional teams to ensure high design quality and drive verification closure.