Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. We are looking for individuals with a background in Design for Testability (DFT) methodologies and implementation for IP/SOC, with demonstrated use and understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687).

MINIMUM QUALIFICATIONS:

• 8+ years of experience in DFT for large and/or mixed-signal ICs
• Understanding of DFT concepts, including scan insertion, BIST, and boundary scan
• In-depth knowledge of DFT EDA tools (Siemens/Synopsys)
• Familiarity with IEEE standards 1149, 1500, and 1687
• Experience with fault simulation and coverage analysis tools
• Knowledge of scripting languages (e.g., Perl, Python) for automation

PREFERRED QUALIFICATIONS:

• Master’s degree in Electrical Engineering or Computer Engineering
• Experience with mixed-signal DFT methodologies, at IP subsystem, SOC, or disaggregated SOCs (2.5D or 3D)
• Experience with hardware testing and debugging

• Develop and implement DFT strategies for data center scale large/disaggregated SOCs, considering factors such as fault coverage, test time, and in-system test
• Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation
• Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns
• Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement
• Generate high-quality test patterns using automated test pattern generation (ATPG) tools
• Verify the correctness of DFT implementation through simulation and hardware testing
• Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process