ASIC Engineer at LinkedIn

berlin, Berlin, Germany -

Full Time

Start Date

Immediate

Expiry Date

15 Jan, 27

Salary

50000.0

Posted On

17 Oct, 26

Experience

1 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Industry

Electrical Equipment Manufacturing

Description

Design and implement RTL modules using SystemVerilog or Verilog.
Translate system-level requirements into hardware architecture, block specifications, and synthesizable RTL.
Develop compute, memory, interconnect, control, and data-movement modules for edge-AI workloads.
Participate in the architecture of mixed-precision AI accelerators supporting FP8, INT8, FP16, BF16, and related numerical formats.
Design high-throughput pipelines for image processing, depth estimation, feature extraction, semantic segmentation, and VLM inference.
Support hardware acceleration for O-HIVE’s 3D spatial-perception and robotic-control pipeline.
AI Accelerator and Memory ArchitectureDesign or integrate matrix multiplication, vector-processing, tensor-processing, and convolution acceleration blocks.
Optimize dataflow for transformer, vision encoder, and multimodal inference workloads.
Develop efficient SRAM, cache, DMA, buffering, and memory-controller architectures.
Analyze model parameters, activation movement, memory bandwidth, and compute utilization.
Support model-to-hardware optimization, including quantization, operator fusion, tiling, sparsity, and memory reuse.
Collaborate with AI engineers to map O-HIVE VLM workloads onto the proposed hardware architecture.
SoC and IP IntegrationIntegrate CPU, NPU, memory, peripheral, security, debug, and interconnect IP.
Support integration of interfaces such as PCIe, Ethernet, MIPI CSI-2, USB, SPI, I²C, UART, GPIO, and high-speed memory.
Support deterministic industrial communication interfaces, including EtherCAT and time-synchronization functions.
Define clock, reset, interrupt, power-domain, and address-map architectures.
Evaluate third-party semiconductor IP and coordinate technical discussions with IP vendors.
Verification and ValidationDevelop block-level and subsystem-level testbenches.
Work with verification engineers on UVM environments, assertions, functional coverage, and regression testing.
Perform RTL simulation, linting, clock-domain crossing analysis, reset-domain crossing analysis, and formal verification.
Support FPGA prototyping and hardware-software co-validation.
Investigate and resolve functional, timing, performance, and integration issues.
Synthesis and Physical-Design SupportPerform logic synthesis, static timing analysis, and design-for-test preparation.
Optimize RTL for frequency, power, area, congestion, and routability.
Collaborate with physical-design engineers on floorplanning, placement, clock-tree synthesis, routing, and timing closure.
Support memory compiler selection, macro placement, power planning, and package-level constraints.
Review PPA results and recommend architectural or RTL-level improvements.
Participate in design reviews leading to tape-out and silicon bring-up.
Power, Thermal, and Performance OptimizationDevelop power-aware RTL and support clock gating, power gating, and dynamic voltage and frequency scaling.
Estimate system power under representative VLM, perception, and robotic-control workloads.
Analyze thermal and power constraints for compact actively cooled edge systems.
Balance compute throughput, memory bandwidth, latency, silicon area, and power consumption.
Support performance modeling before final RTL synthesis and physical floorplanning.
Cross-Functional CollaborationWork closely with O-HIVE’s AI, embedded software, FPGA, PCB, mechanical, robotics, and system-integration teams.
Collaborate with foundries, design-service partners, packaging vendors, and semiconductor IP suppliers.
Support firmware, compiler, runtime, SDK, driver, and board-level development.
Create architecture documents, interface specifications, verification plans, and design-review materials.
Participate in silicon bring-up, characterization, debugging, and production readiness.
Target System ApplicationsThe ASIC platform is expected to support workloads such as:Visual Language Model inference
Transformer and vision-encoder acceleration
RGB and RGB-D image processing
Depth estimation
Object detection and semantic segmentation
Feature extraction and visual localization
3D mapping and spatial understanding
Robot trajectory and motion-planning assistance
Multi-camera and industrial-sensor processing
Real-time control coordination for robotic joints and actuators
Required QualificationsBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Computer Science, or a related field.
Professional or academic experience in ASIC, SoC, FPGA, or digital IC design.
Strong proficiency in Verilog or SystemVerilog.
Understanding of synchronous digital design, pipelining, finite-state machines, memory interfaces, and clock-domain crossing.
Experience with RTL simulation, synthesis, linting, and static timing analysis.
Familiarity with ASIC development tools from Synopsys, Cadence, Siemens EDA, or equivalent vendors.
Understanding of power, performance, and area tradeoffs.
Ability to document technical designs and communicate effectively with cross-functional engineering teams.
Strong analytical, debugging, and problem-solving skills.
Preferred QualificationsExperience designing an NPU, GPU, DSP, tensor accelerator, or AI inference engine.
Experience with transformer, CNN, vision, or multimodal model acceleration.
Knowledge of FP8, BF16, FP16, INT8, quantization, and mixed-precision arithmetic.
Experience with AXI, AMBA, NoC, DMA, SRAM, LPDDR, DDR, or HBM architectures.
Experience with CPU integration, including ARM or RISC-V architectures.
Knowledge of MIPI camera interfaces, Ethernet, PCIe, or industrial communication protocols.
Experience with UVM, formal verification, assertions, and functional coverage.
Experience with FPGA prototyping using AMD/Xilinx, Intel FPGA, or similar platforms.
Familiarity with ASIC physical design, DFT, scan insertion, ATPG, and silicon bring-up.
Experience working with advanced or mature process nodes, including approximately 16 nm or 22 nm.
Familiarity with chiplet, 2.5D, 3D stacking, advanced packaging, or thermal-aware package design.
Understanding of robotics, computer vision, SLAM, depth estimation, or real-time control systems.
Experience coordinating with foundries such as TSMC, Samsung Foundry, or equivalent manufacturing partners.
Initial Engineering ObjectivesThe selected engineer may contribute to the following preliminary development objectives:Define an edge-AI SoC architecture for O-HIVE’s VLM and robotic-perception workloads.
Evaluate mixed-precision compute requirements and achievable throughput.
Develop an initial RTL and FPGA prototype for selected acceleration blocks.
Estimate gate count, SRAM requirements, memory bandwidth, die area, power, and thermal characteristics.
Support architecture exploration across candidate semiconductor process nodes.
Establish a scalable hardware-software platform for future O-HIVE robotics products.
Final specifications, process technology, die dimensions, frequency, memory configuration, and compute capacity will be determined through workload profiling, RTL synthesis, memory compiler selection, and initial physical-design floorplanning.What O-HIVE OffersAn opportunity to design a semiconductor platform specifically for embodied AI and intelligent robotics.
Direct involvement in architecture decisions from initial concept through tape-out and commercialization.
Collaboration with experienced semiconductor, AI, robotics, and industrial-automation leaders.
Exposure to foundry, EDA, packaging, and international technology partners.
A fast-moving environment where engineering work directly influences commercial products.
Competitive salary, equity participation, and performance-based incentives, subject to experience and location.
Application MaterialsApplicants should submit:Resume or curriculum vitae

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