As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
How You Will Contribute:

At Ciena, we are at the forefront of the telecommunications industry, and our Wavelogic modem family of products plays a crucial role in our success. As a Senior Digital Verification Engineer, you will be an integral part of a team responsible for implementing innovative verification strategies in order to thoroughly simulate and validate functional blocks and subsystems for Ciena’s Forward Error Correction (FEC) IP. Reporting to the ASIC Senior Manager, you will collaborate with a team of Digital Design Engineers, Verification Engineers, and Architects to simulate and validate functional blocks and subsystems.

• Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
• Develop verification, functional coverage and formal verification test plans.
• Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.
• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C.
• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function’s designer.
• Provide status updates on verification progress on a regular basis and communicate risks as needed.

Are you passionate about innovation, problem-solving, and working in a collaborative environment? Do you have expertise in Forward Error Correction functions combined with programming proficiency in C++ and SystemVerilog? If so, this role is your chance to make a meaningful impact by contributing to Ciena’s cutting-edge solutions. Join our team and play a pivotal role in driving the future of ASIC testing while shaping the next generation of networking technology.
The above lists are intended to describe the general nature and level of work by the selected candidate. They are not intended to be an exhaustive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

The Must Haves:

• Minimum Bachelor’s degree in Electrical or Computer Engineering.
• Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors.
• Proven ability to determine comprehensive digital verification and coverage strategies.

The Assets:

• Experience with formal verification methods
• Strong background in Forward Error Correction (FEC) and/or DSP.
• Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++.
• Proficiency in bug tracking using Jira and source code management and revision tracking using GIT.

Pay Range: The annual salary for this position is $100,900 - $161,100.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
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At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.
Ciena is an Equal Opportunity Employer, including disability and protected veteran status.
If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require

• Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects.
• Develop verification, functional coverage and formal verification test plans.
• Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods.
• Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C.
• Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function’s designer.
• Provide status updates on verification progress on a regular basis and communicate risks as needed