ASIC Formal Verification Engineer, Google Cloud at Google

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

22 Jul, 26

Salary

198000.0

Posted On

23 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Formal Verification, Design Verification, SystemVerilog, Verilog, Jasper, VC Formal, Questa Formal, 360-DV, ASIC, TPU Architecture, Silicon Bringup, Scripting Languages, Hardware Acceleration, Digital Design, Integrated Circuits

Industry

Software Development

Description

MINIMUM QUALIFICATIONS: * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 4 years of experience with formal and design verification. * Experience with SystemVerilog or Verilog. * Experience working with one or more formal verification tools (e.g., Jasper, VC Formal, Questa Formal, 360-DV). PREFERRED QUALIFICATIONS: * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science. * 6 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based Integrated Circuits (ICs) and chips. * Experience with scripting languages. * Excellent communication and collaboration skills. ABOUT THE JOB: In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to verify the digital designs, with a specific focus on TPU architecture and its integration within AI/ML- driven systems. You will be part of a team developing ASICs used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, formal verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full-time position is $138,000-$198,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google [https://careers.google.com/benefits/]. RESPONSIBILITIES: * Plan the formal verification strategy, create the properties and constraints for the digital design blocks. * Utilize formal property verification tools combined with formal verification closure techniques to verify properties. * Resolve difficult to verify properties. * Contribute improvements to methodologies to enhance formal verification results. * Architect and implement reusable formal verification components.

Responsibilities

You will plan and execute formal verification strategies for digital design blocks, including creating properties and constraints. Additionally, you will contribute to the architecture and verification of next-generation TPU-based data center accelerators.