ASIC Implementation, DFT Engineer at Meta

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

25 Dec, 25

Salary

0.0

Posted On

26 Sep, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Dft, Eda Tools, Scan Insertion, Bist, Boundary Scan, Fault Simulation, Coverage Analysis, Atpg, Scripting Languages, Hardware Testing, Debugging, Mixed Signal Dft, Compliance, Test Pattern Generation, Collaboration, Implementation

Industry

Software Development

Description

Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. The role offers the opportunity to apply your expertise in Design for Testability (DFT) methodologies and IP/SOC implementation. You will leverage and further develop your understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). Responsibilities Develop and implement DFT strategies for data center scale large/disaggregated SOCs, considering factors such as fault coverage, test time, and in-system test Proficiently use Siemens/Synopsys EDA tools for DFT-related tasks, including MBIST, scan insertion, and test pattern generation Ensure compliance with IEEE standards (1149, 1687) for DFT methodologies and test patterns Conduct fault simulation and coverage analysis to assess the effectiveness of DFT strategies and identify areas for improvement Generate high-quality test patterns using automated test pattern generation (ATPG) tools Verify the correctness of DFT implementation through simulation and hardware testing Collaborate with design/implementation teams to ensure that DFT requirements are met throughout the process Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience with 8+ years of experience in DFT implementation Understanding of DFT concepts, including scan insertion, BIST, and boundary scan In-depth knowledge of DFT EDA tools (Siemens/Synopsys) Familiarity with IEEE standards 1149, 1500, and 1687 Experience with fault simulation and coverage analysis tools Knowledge of scripting languages (e.g., Perl, Python) for automation Master's degree in Electrical Engineering or Computer Engineering 14+ years of experience in DFT strategies implementation and development for mixed signal ICs Experience with mixed-signal DFT methodologies Knowledge of scripting languages (e.g., Perl, Python) for automation Experience with hardware testing and debugging

Responsibilities

Develop and implement DFT strategies for large SOCs, ensuring compliance with IEEE standards. Collaborate with design teams to verify DFT implementation through simulation and hardware testing.