Main tasks: 

• You will participate in writing the ASIC microarchitecture specifications
• You will develop the RTL view of some of the ASIC's functions in SystemVerilog, paying particular attention to code quality and genericity.
• You will work closely with:
  • The verification team is responsible for establishing a verification plan, monitoring its implementation, and correcting any issues raised by the verification environment. 
  • The physical design team is working to correct the issues raised by this team, including those related to meeting the target clock frequency and the surface area occupied. 
• You will participate in the validation of the ASIC once it has been manufactured. 

Desired profile:

• Engineering degree or equivalent ( Master's level  or higher) in digital electronics
• Good communication  in a teamwork context, in contact with other teams 
• Rigour, autonomy and good interpersonal skills
• Fluent English (written and spoken, cooperation with English-speaking colleagues)  
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