Synopsys, a world leader in the Semiconductor IP industry, is seeking a Mixed Signal Verification Engineer whose responsibilities are:

PREFERRED TECHNICAL EXPERIENCE:

• Experience in producing high-quality technical documentation is desirable
• Experience with analog tools, preferable Synopsys tools
• Good understanding of analog design
• Experience in Verilog/VHDL
• Proficiency in at least on programming language such as Python, C, C++ and MATLAB
• Experience in System Verilog /VMM/UVM
• Exposure to Unix, Perl and TCL scripting

OTHER QUALIFICATIONS:

• University master’s degree in electronic/Micro-electronics engineering
• 5+ years of relevant experience is highly preferred
• Knowledge of IC design flows
• Analog design knowledge, Digital design understanding
• Analog tools and spice simulators understanding
• Digital verification tools understanding
• Willingness to learn new things.
• Good team-player with organizational and problem-solving skills
• Good English communication skills
  At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things (IOT). These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
  Synopsys’ leading DesignWare IP portfolio is developed by an IP Design Team within Synopsys’ Solutions Group. Part of the Team is in Pavia and is staffed with analog and digital IC design engineers, application engineers and test engineers among others. The company’s extensive IP portfolio enables next-generation SoC designers to integrate silicon-proven functionality previously available only to large integrated device manufacturers. The IP is licensed to leading semiconductor companies across all major markets, offering high-precision, single-function blocks to complete interface sub-systems.

• Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP, having major focus on Analog Schematics
• Debug and verify the Analog schematics, support to Analog teams, to faster verify the functionality of Analog Schematics
• Understand the IP from a System level, Analog and Digital interactions
• Engage in verification activities of analog Designs, under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
• Be able to debug and understand issues related with malfunctions on analog designs
• Exposure to mixed signal validations flow. Co-sim.
• Build productive working relationships, with different teams, cross project
• Participate in applicable product/project reviews.
• Prepare and present reports outlining the outcome of technical projects.