HARDWARE

Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

MINIMUM QUALIFICATIONS

• Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 10 years of experience in advanced packaging with surface mount technology and assembly process development and manufacturing
• In-depth knowledge of flip chip, 2.5D and 3D packaging technologies
• Experience taking products from concept to production including development of manufacturing specifications, vendor qualifications and improvement of manufacturing efficiencies and costs
• Effective communication skills
• Experience working effectively with cross-functional teams
• Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions
• Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors
• Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products
• Lead package development to establish package manufacturability and reliability
• Collaborate with multi-functional teams within Meta and define package requirements

PREFERRED QUALIFICATIONS

• Masters Degree or PhD in Materials Science, Mechanical Engineering, or other related disciplines
• 15+ years of experience in advanced packaging assembly process, SMT
• In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps
• Proven understanding of fanout advanced packaging technologies
• Experience working with ODM, assembly packaging, OSAT, and foundry partners
• Proven technical understanding of full range of semiconductor packaging materials, material interactions, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques
• Familiarity or experience with Finite Element Modeling (FEM) of thermal and thermo-mechanical behavior of packages
• Proven knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI)
• Understanding of package qualification and reliability methods and failure analysis
  For those who live in or expect to work from California if hired for this position.

• Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization to involved in the product definition and optimize chip floorplan, power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology
• Hands on experience in interposer or fanout packages for both organic and inorganic interposer with or without bridges such as Cowos-L, cowos-R, EMIB, embedded fanout bridge from OSAT
• Hands on experience of substrate development and trade off relative to SI/PI, mechanical, thermal and electrical analysis
• Development of advanced packaging technologies (SMT, solder ball attach, and other assembly process) roadmap for AI/ML and networking products applications
• Drive disruptive packaging technologies roadmap to create differentiation for Meta ASICs
• Influence ASIC vendors, foundry and OSATs partners roadmap and align with Meta ASICs roadmap
• Lead development of disruptive advanced packaging technologies from concept to product including Test vehicle definition and building with ecosystem partners
• Drive ecosystem partners for 2.5D/3D and large packages SMT roadmap
• Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging, design feasibility studies and analyses to ensure good manufacturing at ODM
• Participates early on Si/package/PCB/system co-design, and ODM SMT manufacturing work in product development design reviews providing feedback on manufacturability and helps incorporate latest technology advancements and design rules
• Work with internal Si, architecture and system teams and externally engaged partners, ODM, design houses and OSAT companies
• Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package form factor for next generation versions of current products
• Create, conduct, and analyze Design of Experiments (DOE) for development and sustaining activities
• Work cross-functionally with design, NPI, quality and reliability, manufacturing teams and support new technology integration into products
• Support selection, and qualification of external partners (ODM, OEM, OSAT)
• Drafting of SMT assembly and advanced packaging technology definition documentation
• Collaborate with internal and external stakeholders to ensure seamless integration of packaging technology into product development cycles
• Stay abreast of the latest advancements in advanced packaging technologies and market trends
• Identify and evaluate emerging technologies with potential for future applications
• Ability to travel internationally, typically once per quarter