Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

MINIMUM QUALIFICATIONS:

• Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 8+ years of experience in advanced packaging, including surface mount technology, assembly process development, and manufacturing
• Demonstrated experience of flip chip, 2.5D, and 3D packaging technologies
• Proven experience taking products from concept to production, including manufacturing specifications, vendor qualifications, and cost/efficiency improvements
• Experience of cross-functional collaboration skills with internal teams and external partners (silicon, architecture, system, ASIC design, foundry, OSAT, substrate vendors)
• Experience in silicon architecture/package/PCB/system co-design to develop optimal solutions
• Ability to perform design analysis and what-if scenarios for novel packaging schemes to improve bandwidth, power efficiency, and form factor

PREFERRED QUALIFICATIONS:

• Advanced degree (Master’s or PhD) in Materials Science, Mechanical Engineering, or related field
• 10+ years of experience in advanced packaging assembly processes, including SMT
• Demonstrated experience of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, microbumps, and fanout advanced packaging
• Experience collaborating with ODM, assembly packaging, OSAT, and foundry partners
• Technical understanding of semiconductor packaging materials, material interactions, SMT processes, PCB design/layout, failure mechanisms, and analytical techniques
• Familiarity with Finite Element Modeling (FEM) for thermal and thermo-mechanical package behavior
• Knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI)
• Understanding of package qualification, reliability methods, and failure analysis

• Drive chip-package-system co-design optimization for High Performance Computing using 2.5D/3D package technology
• Lead development and roadmap creation for advanced and disruptive packaging technologies (SMT, solder ball attach, assembly processes) for AI/ML and networking products
• Influence and align ASIC vendors, foundry, and OSAT partners’ roadmaps with Meta ASICs roadmap
• Perform package design and feasibility studies for AI/ML and networking applications including single-chip, multi-chip, and SiP/module packaging
• Collaborate cross-functionally with internal teams (Si, architecture, system) and external partners (ODM, design houses, OSATs) to ensure manufacturability and integration
• Conduct design analysis and what-if scenarios for novel packaging schemes to improve package form factor
• Create and analyze Design of Experiments (DOE) for development and sustaining activities
• Stay updated on advanced packaging technologies and market trends, identifying emerging technologies for future applications
• Capacity to travel internationally, typically once per quarter
• Ability to define package requirements and collaborate with multi-functional teams
• Leadership in package development to ensure manufacturability and reliability