ASIC Physical Design Engineer - New College Grad 2026 at NVIDIA

Shanghai, Shanghai, China -

Full Time

Start Date

Immediate

Expiry Date

23 Dec, 25

Salary

0.0

Posted On

24 Sep, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design, Physical Design, RTL Verification, Synthesis, Formal Verification, Timing Closure, Python, TCL, EDA Software, Digital Design, Circuit Design, Chip Integration, Netlist Generation, Methodology Development, Timing Budget, Cross-Team Collaboration, Timing Issues Resolution

Industry

Herstellung von Computerhardware

Description

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, include synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world. What you'll be doing: Chip integration and netlist generation Synthesis, RTL/netlist quality check, Formal Verification Constraints creation and validation, timing budget. Work with ASIC team to analyze/resolve special timing issues. Cross-Team collaboration to implement chip partitioning and floorplan Work in conjunction with PR engineers to achieve timing closure Achieve special mode timing closure, such as io, test, clock, async etc. Function eco creation and method development Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout) Methodology and flow automation development for above areas. What we need to see: MS in EE or Microelectronics Project experience in IC design implementation Courses taken in circuit design, digital design Hand-on experience in EDA software from Synopsys (DC/FC/PT/Formality/ICC2), Cadence (Genus/LEC/Innovus ) is helpful Proficient user of Python or TCL is helpful Proficient in English reading and writing NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, including synthesis, formal verification, constraints definition, and timing closure. You will work on chip integration, netlist generation, and collaborate with teams to resolve timing issues and achieve timing closure.