ASIC Verification Engineer - ARM Remote Job at PDDN INC.

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

15 Jul, 26

Salary

0.0

Posted On

16 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Verification, ARM IP, UVM, SystemVerilog, Cortex-A, Mali GPU, Coresight, Formal Verification, Constraint-random verification, Assertions, Coverage metrics, Gate Level Simulation, RTL, CI/CD, Debugging, Specification review

Industry

IT Services and IT Consulting

Description

Job Description Role: ASIC Verification Engineer - ARM Location: Remote Job Type: Contract Interview: Phone/Skype Job Description: Location: remote Experience : 5 to 8 years with atleast 5 years of strong hands on verification experience Core responsibilities: • Assure the overall quality of our designs, which contribute to exciting launches of wireless portable hardware at Snap • A strong focus on ARM IPs (cpu (cortex-a v9 arch), gpu (mali), debug (css600, coresight), etc.) where your knowledge and experience will allow us to review architectural/design decisions and ramp up on verification of these blocks • Serve as an individual contributor to own and develop the verification of our core IP blocks • Ownership throughout the whole project lifecycle, e.g.: Specification reviews, Verification plans, test case development, UVM environments, Coverage (analysis), Debugging, GLS, etc. • Work closely with other teams to gather relevant information and share your knowledge about the design to further improve requirements and specifications. As well as providing vital feedback in their debugging efforts • Collaborate with the global verification team to improve our processes and launch initiatives to improve the overall quality of the design as well as the way of working to become the best in class verification team Knowledge, Skills and Abilities: • Proven (5+ years) hands-on experience with state-of-the-art verification methodologies and processes, such as UVM / SystemVerilog, Formal verification, Constraint-random verification, Assertions, Coverage metrics, Coverage analysis, Gate Level Simulation, Key Performance Indicators testing, etc. • Strong understanding of ARM related IPs is required: cpu (cortex-a v9 arch), gpu (mali), debug (css600, coresight), etc. • Hands-on experience with designing and implementing C based test-cases to configure and test the ARM IPs as well as the ability to re-use the manufacturer provided test benches • Experience with using and creating a UVM based test environment for block level verification as well as re-using those environments at (sub-)system level • Ability to read and understand RTL code (SystemVerilog, Verilog, VHDL) • Experience with revision control systems and CI/CD techniques • Phenomenal interpersonal skills; ability to collaborate across teams, and to work independently • Excellent process development, documentation and written and verbal communication skills Core responsibilities: • Assure the overall quality of our designs, which contribute to exciting launches of wireless portable hardware at Snap • A strong focus on ARM IPs (cpu (cortex-a v9 arch), gpu (mali), debug (css600, coresight), etc.) where your knowledge and experience will allow us to review architectural/design decisions and ramp up on verification of these blocks • Serve as an individual contributor to own and develop the verification of our core IP blocks • Ownership throughout the whole project lifecycle, e.g.: Specification reviews, Verification plans, test case development, UVM environments, Coverage (analysis), Debugging, GLS, etc. • Work closely with other teams to gather relevant information and share your knowledge about the design to further improve requirements and specifications. As well as providing vital feedback in their debugging efforts • Collaborate with the global verification team to improve our processes and launch initiatives to improve the overall quality of the design as well as the way of working to become the best in class verification team " What are the Optional skills and skill proficiencies for this position? Experience with using and creating a UVM based test environment for block level verification as well as re-using those environments at (sub-)system level • Ability to read and understand RTL code (SystemVerilog, Verilog, VHDL) • Experience with revision control systems and CI/CD techniques • Phenomenal interpersonal skills; ability to collaborate across teams, and to work independently • Excellent process development, documentation and written and verbal communication skills Additional Information All your information will be kept confidential according to EEO guidelines.

Responsibilities

The role involves owning and developing verification for core IP blocks throughout the project lifecycle, including specification reviews, test case development, and UVM environment creation. The engineer will collaborate with global teams to improve design quality and provide feedback on architectural decisions for wireless hardware.