WE ARE:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

• Developing and updating comprehensive test plans and test cases for cutting-edge ASIC products.
• Architecting and writing modular, constrained-random, coverage-driven SystemVerilog and UVM/VMM testbenches.
• Implementing and debugging SystemVerilog assertions (SVA) to ensure design integrity.
• Monitoring simulation regressions, analyzing failures, and troubleshooting issues at both RTL and gate level.
• Performing functional, code, and assertion coverage analysis to maximize verification completeness.
• Tracking and reporting issues using Jira and documenting best practices and findings in Confluence.
• Collaborating with digital and mixed-signal engineers to deliver high-quality test-chip verification results.