ASIC Verification - Team Lead at Microsoft

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

02 Mar, 26

Salary

0.0

Posted On

02 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Verification, Pre-Silicon Verification, Verification Strategies, Test Plans, Verification Environments, Debugging, Performance Modeling, Silicon Debug Tools, Validation Strategy, UVM/SystemVerilog, Coverage-Driven Verification, Digital Design, Computer Architecture, AMBA Protocols, Collaboration, Documentation

Industry

Software Development

Description

Pre-Silicon Verification Improves verification efficiency through new and updated methodologies or tools. Defines verification strategies and test plans. Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels. Drives the development of verification environments, runs, and debugs simulations to drive quality. Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff. Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals. Performance Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs. Determines type of performance model needed and appropriate model fidelity. Leads development of the performance model. Organizes analysis of workload information to identify performance bottlenecks. Collaborates across functions to propose architectural/microarchitectural changes and provide quantitative justification. Leads verification of correlation of system on chip (SoC) performance models to RTL implementation. Post-Silicon Validation Drives development of tools/scripts and guides team to implement silicon debug tools and capabilities, such as crash dumps, register dumps, triggers and tracing, and closed chassis/remote debug. Develops comprehensive, full-chip validation strategy, requirements, environments, tools, and methodologies, including debug board, hardware/software, and lab requirements. Organizes creation of content to run on both bare metal and operating system (OS) environments (e.g., synthetic system on chip (SoC) validation targeting Core, Coherency, Memory, Input/Output (I/O), Accelerators, Security). Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Experience working with large verification projects, including cluster/subsystem and fullchip environments. Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion. Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements. Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification Comfortable and experienced with AI based tools to accelerate productivity. Experience with coverage-driven verification, functional coverage, and code coverage analysis. Execute simulations using industry-standard tools/languages (e.g., SystemVerilog, Perl, C/C++, Assembly, UVM, VCS, Simvision) and analyze results to identify and resolve design issues. Understanding of digital design, computer architecture (ARM, RISC-V, MIPS), and verification methodologies. Familiarity with AMBA protocols (AXI, AHB, APB), ethernet and PCIE interfaces Collaborate with cross-functional teams to define verification scope, coverage goals, and debug strategies. Document verification methodologies, test results, and debug findings for internal reviews and compliance. Participate in design reviews, contribute to architecture discussions, and support post-silicon validation efforts. Debugging skills and ability to work independently in a fast-paced environment.

Responsibilities

The role involves leading the verification of complex flows at various levels, driving the development of verification environments, and ensuring quality through effective methodologies. Additionally, it includes post-silicon validation and the development of comprehensive validation strategies and tools.