JOB DESCRIPTION:

Airbus Defense & Space is looking for an

BACHELOR’S/MASTER’S THESIS: STUDENT (D/F/M) IN THE FIELD OF ENGINEERING FOR SPACE MECHANISMS ALGORITHMS - VHDL DEVELOPMENT INTO A STANDARDIZED, SPACE-QUALIFIED IP CORE

Are you looking for an interesting topic? Would you like to discover the work of a digital development engineer (d/f/m) at Airbus Defence and Space?
Then apply now! We look forward to you joining us!

You will have the opportunity to become a member of the space mechanism department, working in close collaboration with the engineers with a focus on mechatronics and electronics. The focus of the thesis will be space grade motor control electronics.

• Location: Friedrichshafen
• Start: 01.11.2025
• Duration: 6 months

DESIRED SKILLS AND QUALIFICATIONS

• Enrolled full-time student (d/f/m) in the area of Electrical Engineering, Telecommunication Engineering, Space Engineering or an equivalent field of study.
• Good basic knowledge in VHDL and FPGA development.
• Structured way of working.
• You are a good team player, have excellent communication skills, and are able to work independently.
• Solid capabilities and interest in documentation of work.
• Languages: English is mandatory; French or German would be an asset.
  Please upload the following documents: cover letter, CV, relevant transcripts, enrollment certificate.
  Not a 100% match? No worries! Airbus supports your personal growth.
  Take your career to a new level and apply online now!
  This job requires an awareness of any potential compliance risks and a commitment to act with integrity, as the foundation for the Company’s success, reputation and sustainable growth.

EXPERIENCE LEVEL:

Student

• Analysis and understanding of the existing development.
• Learn and understand formal development requirements from ESA standard.
• Definition of external interfaces of module interfaces together with Airbus engineers.
• Formalize requirements into a VHDL IP-Core specification.
• Check existing VHDL code against coding standards.
• Delta-development of module with respect to defined interfaces and coding standards.
• Definition and development of test-benches and test-cases.
• Perform anonymization of developed IP-Core.
• Perform verification and validation of IP-Core.
• Documentation of development and IP-Core according to ESA standard in English language.