Backend ASIC/FPGA Engineer at ARQUIMEA

Madrid, Community of Madrid, Spain -

Full Time

Start Date

Immediate

Expiry Date

29 Jul, 26

Salary

0.0

Posted On

30 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC design, FPGA design, Logic synthesis, Place and route, Timing closure, Static timing analysis, Floorplanning, Clock tree synthesis, Tcl, Python, Bash, Mixed-signal integration, Physical verification, Constraint development, Hardware bring-up, SystemVerilog

Industry

Defense and Space Manufacturing

Description

ARQUIMEA, we are a technology company operating globally and providing innovate solutions and products in highly demanding sectors. Our areas of activity are Aerospace, Defense & Security, Big Science, Biotechnology and Fintech. Main function and scope: · Backend ASIC/FPGA Engineer – Synthesis, Place & Route, and Timing Closure Core functions: · Own and execute backend implementation flows for ASIC and/or FPGA designs. · Perform logic synthesis, constraint development, optimization, and design quality checks. · Run place and route flows, including floorplanning, placement, clock tree synthesis, routing, and physical optimization. · Drive static timing analysis and timing closure across multiple modes and corners. · Analyze and resolve timing, congestion, area, power, and signal integrity issues. · Develop, review, and maintain timing constraints, including SDC/XDC files. · Support backend sign-off activities such as timing, power, DRC/LVS, CDC/RDC, and equivalence checking, depending on project scope. · Support mixed-signal integration activities, including coordination between analog and digital implementation flows. · Work with analog designers on floorplanning, pin planning, power domains, guard rings, keep-outs, substrate noise considerations, and analog/digital interface constraints. · Support the integration of analog macros, hard IP blocks, memories, PLLs, ADCs, DACs, sensors, or other mixed-signal IP. · Collaborate with frontend RTL designers to improve implementation quality and resolve design issues. · Work with FPGA flows including synthesis, implementation, timing analysis, bitstream generation, and hardware bring-up support. · Contribute to automation scripts and flow improvements using Tcl, Python, Bash, or similar scripting languages. · Participate in design reviews and provide technical input on architecture, feasibility, performance, power, and area trade-offs. · Support requirements analysis, traceability, and verification alignment where applicable. Required experience and candidate profile: -Telecommunications engineering, electronic engineering or equivalent. -A master in micro-electronics or applicable experience in the field. -+5 years of experience in back-end ASIC/FPGA design Technical Requirements: Training / specific knowledge required in: · Professional experience in ASIC and/or FPGA backend implementation. · Strong knowledge of digital implementation flows, including synthesis, place and route, and timing closure. · Experience with static timing analysis and constraint definition. · Familiarity with industry-standard EDA tools for ASIC and/or FPGA implementation, such as Synopsys, Cadence, Siemens EDA, Xilinx/AMD Vivado, or Intel Quartus. · Good understanding of clocking, reset strategies, timing exceptions, CDC considerations, and low-power design concepts. · Ability to debug timing, congestion, utilization, routing, and implementation issues. · Understanding of mixed-signal design integration challenges, especially analog/digital interfaces, floorplanning constraints, power integrity, noise coupling, and physical verification implications. · Scripting experience with Tcl, Python, Bash, Perl, or similar. Nice-to-have training / specific knowledge: · Experience with frontend RTL design using VHDL, Verilog, or SystemVerilog. · Experience supporting mixed-signal ASIC designs with analog macros or custom IP. · Experience with requirements management, traceability, and requirements-based verification. · Knowledge of safety-critical or high-reliability development flows, such as aerospace, automotive, defense, or space applications. · Familiarity with ECSS, or similar standards. · Experience with formal verification, linting, CDC/RDC analysis, logic equivalence checking, or power analysis. · Experience with DRC/LVS debugging, parasitic extraction, IR drop analysis, EM analysis, or physical sign-off. · Experience with FPGA prototyping, lab debugging, board bring-up, or hardware validation. · Knowledge of high-speed interfaces, embedded processors, SoCs, DSP blocks, memory controllers, PLLs, ADCs, DACs, or sensor interfaces. · Experience developing reusable implementation flows and automation infrastructure. The position is located at our headquarters in Madrid, at Calle Serrano Galvache, 56. We're looking for curious, creative, tenacious and collaborative people, eager to do things and unafraid to tackle challenges in order to contribute to improving the society in wich we live. Think Big, Do the Job & Enjoy Life At ARQUIMEA, we value diversity and inclusion. We do not discriminate on the basis of race, color, religion, gender, sexual orientation, gender identity, national origin, age, disability, or other protected factors by law. All candidates will be considered equally based on their skills and experience

Responsibilities

The engineer will own and execute backend implementation flows for ASIC and FPGA designs, including synthesis, place and route, and timing closure. They will also collaborate with analog and frontend teams to resolve design issues and support physical sign-off activities.