CAD Engineer - Timing for Gate-Level Flows & Methodologies at Apple

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

22 Jan, 26

Salary

0.0

Posted On

24 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, Python, Tcl, CAD Flows, Automation, SoC Designs, Deep Sub-Micron Technologies, Noise, Cross-Talk, Variation, Timing Models, Timing Constraints, Post-Silicon Timing Debug, Communication, Debugging, Methodologies

Industry

Computers and Electronics Manufacturing

Description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon. DESCRIPTION As a member of our STA CAD team, you will:
• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems MINIMUM QUALIFICATIONS Minimum requirement of BS and 10 years of relevant industry experience. PREFERRED QUALIFICATIONS Expert power user of static timing analysis tools and flows Advanced programming skills with Python and Tcl or other high level programming languages Proven track record of development and deployment of complex CAD flows and automation Familiar with STA of large high-performance SoC designs in deep sub-micron technologies Deep understanding of noise, cross-talk, variation, margins, and timing models Knowledge of timing/SDC constraints, hands on experience in creation and validation of constraints Excellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Responsibilities

You will develop, maintain, and enhance existing gate-level static timing analysis flows for Apple silicon designs. Additionally, you will work with design teams to address timing challenges and improve overall STA methodologies.