CAD Logic Equivalence Checking (LEQ) Engineer at Apple

Haifa, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

12 Aug, 26

Salary

0.0

Posted On

14 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Logical Equivalence Checking, RTL Design, Synthesis, Netlist Transformations, Low-power Design, UPF, Cadence Conformal, Synopsys Formality, TCL, Python, VLSI, SoC, PnR Flows, ECO Flows, Sign-off Methodologies, Debugging

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Multifaceted, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Apple’s CAD Hardware Tech team are responsible for automating processes in designing Apple’s chips which power everything from Apple Watch and Apple TV to iPhone and iPad. We have outstanding career opportunities for interns interested in applying their software knowledge towards developing Apple’s ground breaking methodologies. Working among the industry's best, we’re looking for those with talent and ambition to innovate the way we design computer chips, to provide the next technological leap and improve customer experiences. DESCRIPTION We are seeking a CAD LEQ (Logical Equivalence Checking) Engineer to develop, deploy, and support equivalence checking methodologies across complex SoC programs. This role focuses on ensuring functional correctness between RTL, synthesized netlists, and post-implementation designs, while driving scalable, robust sign-off flows. MINIMUM QUALIFICATIONS BSc/MSc in Electrical Engineering or Computer Science 5+ years of experience in VLSI industry Strong understanding of: RTL design, Synthesis and netlist transformations, low-power design ( UPF concepts) Hands-on experience with LEQ tools ( Cadence Conformal , Synopsys Formality ) Strong debugging and scripting skills ( TCL, Python ) PREFERRED QUALIFICATIONS Experience with power-aware LEQ and low-power verification flows Familiarity with synthesis and PnR flows Experience in large-scale SoC environments and multi-site collaboration Exposure to ECO flows and late-stage sign-off methodologies Experience working with EDA vendors and driving tool improvements

Responsibilities

Develop, deploy, and support equivalence checking methodologies to ensure functional correctness across complex SoC programs. The role involves driving scalable sign-off flows between RTL, synthesized netlists, and post-implementation designs.