Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something - you’ll add something.

DESCRIPTION

Do you love elegant crafting solutions to highly sophisticated challenges? Do you intrinsically see the importance in every detail? As a member of our dynamic Cellular group, you’ll be at the heart of chip design! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. This is a high visibility and mission critical role, which provides excellent exposure to multiple VLSI design technologies and flows. This role requires a strong foundation of digital design and VLSI fundamentals. It also requires close working relationships with many functional teams. ON OUR TEAM YOUR RESPONSIBILITIES WILL INCLUDE: - Contributing to definition, architecture, design and development of cellular sub system. - Performing all aspects of front-end design flow including integration, power analysis, design checks, verification reviews, review synthesis, timing constraints. - Performing power analysis and analysis different design tradeoffs and drive power improvements. - Developing design methodologies for scalable designs. - Providing pre/post silicon debug support.

MINIMUM QUALIFICATIONS

• Minimum requirement of a bachelors degree.
• Knowledge of the ASIC design flow, FE, Low power design and design verification, scripting.
• Knowledge of ASIC/SoC design flow.
• Knowledge of FE tools (CDC, RDC, LINT, Formal, LP Checks, LEC, PTPX).
• Knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.)
• Analytical skills to be able to make design tradeoffs for best performance, low area, and low power.
• Knowledge of power analysis tools/flows and UPF flow for defining power intent of chips with multiple power domains.
• Understanding of version control tools and handoff of design releases.
• Understanding of scripting skills to automate tasks and build scalable design flows.
• Understanding of synthesis and STA constraints.

PREFERRED QUALIFICATIONS

• Familiarity with DFT, MBIST, Synthesis, STA and backend related methodology and tools.

Please refer the Job description for details