The Display Silicon & Electronic Architecture team, within the broader Display and Optics organization, is seeking a CMOS Process Integration Engineer to support the development and integration of Meta’s proprietary display silicon backplanes for wearable AR displays. In this role, you will collaborate closely with silicon architects, III-V device and process engineers, electrical engineers, optical scientists, the visual quality team, and external foundries to develop and deliver silicon display process integration solutions. This role provides a unique opportunity to contribute to both forward-looking research and product-critical projects, requiring collaboration across multiple teams within Meta Reality Labs.

MINIMUM QUALIFICATIONS:

• Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• M.S. or Ph.D. degree in Electrical Engineering, Materials Science, Chemical Engineering, Physics, or in a related field
• 10+ years of industry experience working in a CMOS Process Engineering function
• Direct experience in technologies including: 3-D integration, µTSV, hybrid bonding, wafer reconstitution, and pick-and-place
• Experience leading cross-functional teams and collaborating with external partners
• Demonstrated experience communicating and presenting to highly cross functional group of partners
• Experience leading programs and setting direction proactively with limited guidance

PREFERRED QUALIFICATIONS:

• Ph.D. degree with a focus on CMOS Process Integration
• Experience with heterogeneous integration technologies (e.g. III-V, silicon photonics, etc.)
• Direct experience with displays, especially silicon-based microdisplays
• Keen interest in emerging AR/MR display technology

• Drive the CMOS process integration roadmap, working closely with foundry partners and our downstream technology partners
• Define process flows and technical requirements to improve form factor & enable functional improvements in our novel silicon-based microdisplays
• Operate as a leader in a highly collaborative, cross-functional role
• Communicate efficiently and effectively with partners and organizational leadership
• Define architecture specification and align requirements with partners
• Up to 15% travel (domestic and international)