Requirements

• University degree, Diploma or BS EE
• Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle
• Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog)
• Experience with standard simulation tools for digital designs
• Basic knowledge about UNIX* or Linux* environment and using programming languages
• Technical communication, team work and problem solving skills
• English language skills