PREFERRED EXPERIENCE:

• Engineering DevOps/Infrastructure development experience modernizing and maintaining industry leading engineering infrastructure
• Strong proficiency with scripting such as Python, Perl, Ruby, Shell and/or TCL
• Verilog RTL development with industry tools in a CPU, SOC or ASIC environment
• Demonstrates expertise in the following:
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• Engineer Infrastructure development and ownership of in-house engineering tools

• Automation of engineering flows and tools
• RTL linting tools to analyze RTL code.
• Design methodologies and tools to aid and improve RTL design quality
• Processor architecture including high-performance out-of-order processor architecture
• Logic design
• RTL coding experience for a high-speed processor
• Power-saving and energy efficient design techniques
• Exposure to physical design and verification methods
• Ability to work with performance team and debug and fix performance issues
• Awareness of synthesis, place and route, and timing closure concepts
• Development experience from clean-sheet design to product tapeout to post-silicon debug
• Proven experience with microarchitecture development, as demonstrated by patents, publications, product features
• Strong problem-solving and debugging skills

• Other software development experience

  Background in other aspects of ASIC implementation, especially with synthesis flow and static timing analysis

• Knowledge of microprocessor Design-for-Test (DFT) and Design-for-Debug (DFD) logic and issues

• Experience in clocking, reset, power-up sequences and power management
• Experience with x86 or ARM Architecture (ISA)

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

As an RTL Infrastructure Engineer, you will have a unique opportunity to work on both the functional RTL of AMD’s next-generation core and the infrastructure and tooling that streamlines the full Core RTL team’s efficiency and productivity. You will work in the center of an experienced, skilled, and motivated engineering team with a track record of success. As a member of the Core RTL team, you will work on the leading edge of processor technology and
collaborate with the Performance Modeling, Design Verification, Physical Design, and Post-Silicon Teams to make AMD’s ambitious future CPU roadmap a reality.

KEY RESPONSIBILITIES:

• Execute and refine methodology and tools needed to accomplish RTL design work
• Collaborate with a team of hardware and infrastructure engineers to develop best in class engineer infrastructure for RTL development
• Execute on RTL design and coding for various sections of the processor core pipeline and related logic
• Participate in the definition of microarchitecture of next-generation high-performance processor cores
• Contribute to design verification, performance verification, synthesis, power reduction, timing convergence, and floorplan efforts
• Contribute to silicon debug and product support as needed