CPU Design Timing Engineer at Apple

Beaverton, Oregon, United States -

Full Time

Start Date

Immediate

Expiry Date

10 Sep, 26

Salary

0.0

Posted On

12 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Synthesis, Place-and-Route, Clock Flow, PPA Optimization, CPU Physical Design, Static Timing Analysis, Critical Path Closure, CPU Microarchitecture, Low Power Implementation, Process Technology Evaluation

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation. DESCRIPTION As an CPU Technology Feasibility Implementation Engineer, you will be working on technology evaluation in the early design phase. You will be responsible for conducting experiments and analysis on process technology in CPU physical design and find out how to maximize PPA benefit from technology. Responsibilities include, but are not limited to: • Understanding new process technology and PPA trends • Driving RTL-to-GDS flow through synthesis/place-and-route for technology evaluation experiments • Analyzing PD results and identifying areas for improvements to maximize PPA benefit by new processes in all scopes such as technology, library/memory design, PD tools/methodology, RTL, etc. • Working with multi-functional engineering teams to resolve technology-related issues or improve PPA further • Performing and analyzing various PD experiments with new process technology to understand how to achieve high targets for performance, power, and area MINIMUM QUALIFICATIONS Minimum BS and 10+ years of relevant industry experience Experience with synthesis, PnR and clock flow, and PPA optimizations PREFERRED QUALIFICATIONS The ideal candidate will have implementation experience on high-performance CPU designs Deep understanding of process technology and its evaluation Deep understanding of power, performance, and area tradeoffs Deep knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs Understanding of static timing and critical path closure techniques

Responsibilities

The engineer will evaluate process technology in the early design phase to maximize power, performance, and area (PPA) benefits. This includes driving RTL-to-GDS flows and collaborating with multi-functional teams to resolve technology-related issues.