CPU Hardware Validation Engineer (Intern position) at Intel
Guadalajara, Jal., Mexico -
Full Time


Start Date

Immediate

Expiry Date

29 Apr, 25

Salary

0.0

Posted On

30 Jan, 25

Experience

0 year(s) or above

Remote Job

No

Telecommute

No

Sponsor Visa

No

Skills

Python, Written Communication, C, Java, Communication Skills, Computer Science, C++, Computer Engineering, Programming Languages

Industry

Information Technology/IT

Description

JOB DESCRIPTION

The world is transforming and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth.
You will be part of the Power and Performance (PnP) validation team and have an impact on Intel’s next generation. Responsibilities include understanding CPU architecture, PnP optimization, as well as identifying further opportunities to close the gap with respect to pre-silicon targets. In this position, you will collaborate closely with architects and designers to validate power and performance features.

A SUCCESSFUL CANDIDATE WILL HAVE PROVEN EXPERIENCE DEMONSTRATING THE FOLLOWING SKILLS AND BEHAVIORAL TRAITS:

  • Self-discipline and good collaboration within or across team.
  • The ideal candidate will demonstrate good problem-solving skills.
  • Communication skills in both verbal and written communication.

MINIMUM QUALIFICATIONS:

Minimum qualifications are required to be initially considered for this position.

  • You must be enrolled in a Bachelor’s or Master degree in Computer Engineering, Computer Science or Electrical/Electronic Engineering, or related fields.
  • Advanced English level.
  • 3+ months working with programming languages such as Python, C, C++ or Java.
  • 3+ months experience with Excel and MS Office package.

Experience listed below would be obtained through relevant previous schoolwork, internship, jobs and/or research experience.

Responsibilities
  • Understanding silicon parametric across distributions (Vmins, Cdyn, leakage, transistor performance, etc.) and their impacts on CPU power and performance.
  • Understanding of workloads, benchmarking, and TDP power recipes.
  • System-level understanding of power management flows at the hardware, firmware, and driver levels.
  • Analysis of silicon performance power consumption versus pre-silicon expectations and drive resolution of issues in simulation, emulation, and system platform.
  • Close interface with architecture, design, and platform engineers.
  • Contributing towards power management optimization flows for future products.
Loading...