CPU Implementation Engineer at Apple

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

12 Jul, 26

Salary

0.0

Posted On

13 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

CPU implementation, RTL-to-GDS, Synthesis, Place-and-route, TCL, Perl, Logic design, Digital circuits, Microprocessor architecture, STA, Power analysis, Floor-planning, Pin-placement, Timing budgeting, Communication skills

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation. DESCRIPTION As a CPU Implementation Engineer, you will drive or participate in the following: • Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs • Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA • Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield • Work closely with internal CAD and PD methodology teams on industry-standard synthesis/PNR tool features and optimizations and their adoption in CPU design • Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability • Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA MINIMUM QUALIFICATIONS Minimum BS Experience in TCL or Perl PREFERRED QUALIFICATIONS Logic design and digital circuits knowledge Familiarity with high performance CPU microprocessor architecture Experience in using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with floor-planning, pin-placement and timing budgeting Ability to work well in a team, self-motivated, and excellent communication skills

Responsibilities

You will drive RTL-to-GDS design convergence and optimize microarchitecture for power, performance, and area. Additionally, you will collaborate with cross-functional teams on CPU floorplanning, timing, and electrical requirements.