CPU Physical Design and Integration Engineer at Apple

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

12 Jul, 26

Salary

0.0

Posted On

13 Apr, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, CPU Integration, Place and Route, Physical Verification, Floorplanning, Perl, Tcl, Python, CMOS Circuit Design, Clock Design, Extraction, STA, EMIR Methodology, DRC/LVS Verification, Chip Layout, CAD

Industry

Computers and Electronics Manufacturing

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! Dynamic, thoughtful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a processor design effort collaborating across domains, with a critical impact on getting functional products to millions of customers quickly. DESCRIPTION As a CPU Physical Design and Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development. • Full chip floorplan, area optimizations, block partitioning and pin placements • Own chip level place and route (PnR), final CPU layout database construction, and verification (PDV) • Evaluate route ability, power grid and technology bring up • Drive custom layout integration and IPs for CPU • Work with the Implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout • Work with the SOC team to meet IP technical and delivery requirements • Participate in establishing CAD and physical design methodologies • Participate in flow development for chip integration and analysis • Scripting to automate tasks and improve debug efficiency MINIMUM QUALIFICATIONS Minimum BS and 3+ years of relevant industry experience Experience with place and route and physical verification Experience with a scripting language such as Perl or Tcl PREFERRED QUALIFICATIONS Knowledge of industry standard place and route tools and practices in physical design, including floor planning Experience in physical construction, integration, PDV, DRC/LVS verification Experience in partitioning, budgeting, pin planning Working knowledge of Python Solid understanding of CMOS circuit design Working knowledge of clock design and physical implementation of custom clocks Layout design background is a plus Working knowledge of extraction, STA, EMIR methodology, and tools Ability to work well in a team, being an excellent problem solver, and self-motivated

Responsibilities

You will be responsible for the physical design, integration, and verification of high-performance, low-power processors. This includes managing full-chip floorplans, place and route, and driving signoff closure for tapeout.