CPU power estimation and optimization at Advanced Micro Devices, Inc

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

27 Aug, 26

Salary

0.0

Posted On

29 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

CPU Micro-architecture, Power Modeling, Power Estimation, PPA Tradeoffs, RTL Power Analysis, DVFS, ISA Extensions, Power Correlation, Technical Leadership, Architectural Analysis, SRAM, Cache Structures, ML-assisted Estimation, Physical Design, Workload Analysis, CPU Power Architecture

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Section Description (CPU‑Focused, SMTS Scope) Role Objective Act as the technical lead for CPU power estimation and optimization, shaping power strategy for high‑performance CPU cores . Deliver credible power projections from early architecture through sign‑off and influence CPU design decisions across multiple generations. CPU Power Architecture Leadership • Define CPU power architecture including core, cache (L1/L2/L3) • Establish voltage domains power goals for each states, performance states, low‑power modes, and CPU use‑case power envelopes • Drive power‑performance‑area (PPA) tradeoffs for different goals for CPU units Architectural Feature Power Analysis (CPU) • Quantify power cost of CPU micro‑architectural features (pipeline depth, width, speculation, cache structures, predictors, queues, buffers) • Evaluate power impact of ISA extensions, frequency targets, and workload characteristics • Use prior‑generation CPU data to guide next‑generation architectural decisions CPU Power Estimation Strategy • Own early CPU power estimation using architecture‑level parameters (flops, SRAM bits, activity proxies, frequency, topology) • Define correlation strategy from early estimates → RTL power → physical implementation → silicon • Ensure estimates are actionable for CPU architecture and program planning decisions Modeling & Methodology Development • Develop and maintain CPU‑specific power models at core and CCX • Drive scalable estimation frameworks (analytical, statistical, or ML‑assisted) suitable for early CPU planning • Standardize CPU power estimation methodologies across teams and programs Cross‑Functional Technical Leadership • Partner with CPU Architects, RTL, Physical Design, CAD, and Platform teams to drive power‑informed decisions • Serve as reviewer for CPU power assumptions and estimates used in exec and design reviews • Mentor senior engineers in CPU power modeling and estimation techniques CPU Power Optimization & Direction Setting • Identify architectural power‑reduction opportunities across core and uncore • Influence CPU roadmap decisions with quantified power impact and risk assessment • Balance peak performance goals with sustainable power efficiency System & Workload Awareness • Ensure CPU power models reflect realistic workloads (client, server, AI, mixed workloads) • Account for DVFS behavior, boosting, throttling, and residency in CPU power estimates Deliverables & Impact • CPU power architecture definitions adopted across multiple programs • Trusted early power estimates that meaningfully predict late‑stage and silicon power • Architectural tradeoff analyses that directly influence CPU design choices Required Experience • Deep expertise in CPU micro‑architecture and power drivers • Strong background in power modeling, estimation, and correlation for high‑performance CPUs • Proven ability to influence architecture decisions using quantitative power analysis PMTS Expectations • Recognized company‑wide expert in CPU power. • Sets technical direction beyond own team or project • Solves ambiguous, multi‑team CPU power challenges • Work impacts multiple CPU generations or product lines Preferred Background • Advanced‑node CPU design experience • Pre‑silicon to post‑silicon power correlation experience • Experience defining reusable CPU power methodologies adopted at scale #LI-Hybrid #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Act as the technical lead for CPU power estimation and optimization, shaping power strategy and delivering projections from early architecture through sign-off. Drive PPA tradeoffs and develop scalable power models to influence CPU design decisions across multiple generations.