CPU Verification Engineer - Unit DV at Advanced Micro Devices, Inc

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

04 Jul, 26

Salary

0.0

Posted On

05 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

CPU Verification, SystemVerilog, UVM, C++, Python, RTL, Out-of-order Execution, Cache Coherence, Memory Ordering, VCS, Verilator, Test Planning, Coverage Closure, Emulation, Post-silicon Validation, Scripting

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The person will be part of AMD's CPU Performance Validation team. This team is part of AMD's global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It’s always We before Me in the team THE ROLE: We are seeking a highly skilled Verification Engineer who can carry out cutting-edge unit-level verification for complex CPU designs. You will own the creation of comprehensive test plans, drive coverage closure, and collaborate closely with RTL designers to resolve issues and achieve tape-out readiness. Beyond simulation, you will support emulation and post-silicon validation efforts, while setting best practices and mentoring junior engineers to elevate the team’s verification capabilities. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Experienced verification engineer with deep expertise in high-performance CPU verification. Proven track record in developing scalable verification environments, driving coverage closure, and collaborating across architecture, RTL, and post-silicon teams. Key Responsibilities Architect and implement unit-level verification environments using C++/SystemVerilog/UVM Develop detailed test plans for functional and performance verification of Load/Store, Scheduler, and Execute Units Create directed and random stimulus, checkers, and coverage models Debug simulation failures and collaborate with RTL designers to resolve issues Drive coverage closure and ensure high-quality tape-out readiness Support emulation and post-silicon validation efforts Mentor junior engineers and contribute to verification best practices Qualifications Strong understanding of out-of-order execution, memory ordering, and cache coherence Proficiency in SystemVerilog, UVM, C++, Python Experience with x86, ARM, or RISC-V architectures Familiarity with simulation tools (VCS, Verilator), waveform debugging, and scripting etc Excellent problem-solving and communication skills #LI-BM2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The engineer will architect and implement unit-level verification environments for complex CPU designs using C++, SystemVerilog, and UVM. They will also drive coverage closure, debug performance issues, and collaborate with RTL designers to ensure tape-out readiness.