DDR Interface Evaluation Leader at Renesas Electronics

Kodaira, , Japan -

Full Time

Start Date

Immediate

Expiry Date

01 Jul, 26

Salary

0.0

Posted On

02 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

DDR Interface Evaluation, LPDDR4/5/6, DDR PHY, Margin Analysis, Stress Testing, Root-cause Analysis, Analog Behavior, PLL, Jitter, Noise Analysis, SI/PI, Power Integrity, Technical Leadership, Automotive SoC, Oscilloscope, Logic Analyzers

Industry

Semiconductor Manufacturing

Description

Job Description 【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Within such SoCs, the DDR interface is a critical component that directly impacts system stability and performance. Ensuring reliable operation through silicon‑level evaluation, margin analysis, and stress testing is essential, particularly as SoCs become more highly integrated and operate at higher performance levels. We are therefore seeking a technical leader who can leverage hands‑on experience in DDR interface evaluation to work closely with design teams and IP vendors, and lead evaluation activities with sound technical judgment. This role is expected to contribute to overall development by using evaluation as a starting point to support quality improvement across the SoC. 【Job Description】 Lead the technical execution of DDR interface evaluation for automotive SoCs (R-Car series). - Target examples include LPDDR4X / 5 / 5X / 6, DDR PHY, and memory‑controller‑related interfaces. Drive silicon and board‑level evaluation, margin analysis, stress testing, and compliance with standards and internal guidelines, ensuring the quality and reliability of the DDR interface. Define and align evaluation strategy, design test items and conditions, and consolidate evaluation results into clear outputs. When issues arise, collaborate with design teams, SoC teams, and IP vendors to perform root‑cause analysis and drive countermeasure planning. Provide technical leadership to evaluation and design members across Japan, India, and Vietnam, clarifying evaluation flow and decision criteria to improve overall quality. ※The full details regarding your position scope as well as any future potential changes in work location and job scope will be provided during the interview process. Qualifications 【MUST】 Hands‑on experience in evaluation or verification of DDR interfaces (e.g., LPDDR4/4X/5). Experience in issue analysis, root‑cause investigation, and countermeasure discussion based on margin testing and stress evaluation. Ability to organize evaluation results and conduct technical discussions and alignment with design teams and stakeholders. Knowledge or experience related to analog behavior and characteristics relevant to DDR interfaces (e.g., DDR PHY, PLL, jitter, noise, SI/PI, power integrity). Ability to collaborate technically in English with design sites in India and Vietnam, as well as IP vendors. 【WANT】 Experience leading or co‑leading evaluation activities for DDR PHY, memory controllers, or board‑level DDR interfaces. Experience in measurement and analysis of DDR signals, timing, and power behavior using lab equipment (e.g., oscilloscopes, logic analyzers). Experience coordinating with external IP vendors on technical inquiries, issue alignment, and sharing of evaluation results. Experience in automotive SoC projects or in products requiring high levels of quality and reliability. Interest in expanding contribution beyond DDR evaluation into broader cross‑functional collaboration with design and SoC teams. Japanese language proficiency at a conversational level Additional Information If you are interested in this position, please feel free to contact us at the details below: Recruiter:Masana Ueno ルネサスは、「To Make Our Lives Easier 」（人々の暮らしを楽“ラク”にする）というPurposeの下、組み込み半導体ソリューションを提供します。高品質とシステムレベルノウハウを兼ね備えた組み込み半導体のリーダーとして、自動車、産業、インフラ・IoT分野向けに、ハイパフォーマンスコンピューティング、組み込みプロセッシング、アナログ＆コネクティビティ、そしてパワーを含めた幅広い製品ポートフォリオを軸とした、スケーラブルで包括的なソリューションを提供しています。ルネサスは、30か国以上で22,000 人を超える多様性あふれる従業員と共に、限界に挑戦しながら、デジタライゼーションを通じてユーザエクスペリエンスを充実化させ、新たなイノベーションの時代を切り開いていきます。そして世界中の人々やコミュニティの未来のために、持続可能で省エネ効果の高いソリューションの開発に全力で取り組み、「To Make Our Lives Easier」を実現します。ルネサスで実現できることキャリアをスタート、そしてキャリアアップ：4つのプロダクトグループをはじめ、さまざまな部門において技術職として、また幅広いビジネスの経験を積むことができます。ハードウェア、ソフトウェアの専門知識を深めたり、新しいことにチャレンジしたりする機会があります。やりがいとインパクトのある仕事をする：革新的な製品とソリューションの開発に関わることにより、世界中のお客様のニーズに応えると同時に、人々の生活をより便利で安全かつ安心なものにすることに貢献できます。「ウェルビーイング」に焦点を置いた環境で最大限に能力を発揮する：ルネサスでは、リモートワーク制度などによる柔軟な勤務体制づくり、また従業員リソースグループの積極的な活動をサポートするなど、インクルーシブな職場環境構築を目指しています。従業員を第一に考えたカルチャーとグローバルなサポート体制が、入社後すぐに活躍できる環境を提供します。自分の力で成功を掴み、キャリアを築く準備はできていますか？ルネサスで一緒に未来を形づくっていきましょう。当社では、ハイブリッド勤務モデルを採用しており、従業員は週に2日間リモートワークを行うことができます。同時に、残りの日はチームとしてオフィスに集まり、協働を強化しています。出社指定日は火曜日から木曜日で、イノベーション、コラボレーション、そして継続的な学習に取り組む日としています。 Employment Type: Regular (PERM) Remote Work Available: No

Responsibilities

Lead the technical execution of DDR interface evaluation for automotive SoCs, including margin analysis and stress testing. Collaborate with design teams and IP vendors to perform root-cause analysis and provide technical leadership across global development sites.