Debug SoC Design Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

28 Jan, 26

Salary

0.0

Posted On

30 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Debug Features, SoC Architecture, Digital Design, Verilog, ASIC Design Flow, Microprocessor Debug, CoreSight, Micro-Architecture Specifications, AXI/AHB Bus Fabric, Low-Power Design, Design Methodologies, EDA Tools, Collaboration, Validation Engineering, Trace Hub Design, Self-Starter

Industry

Computers and Electronics Manufacturing

Description

Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. DESCRIPTION In this role you will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers. MINIMUM QUALIFICATIONS BS with 3+ years relevant experience. Familiarity with the ASIC design flow. Knowledge of digital design, SoC architecture, and HDL languages like Verilog. Familiarity with design methodologies and industry standard EDA tools. PREFERRED QUALIFICATIONS Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques. Shown experience writing micro-architecture specifications and converting them to design. Experience with AXI/AHB bus fabric and processor sub-systems. Understanding of UPF and low-power design & implementation techniques. Self-starter and willingness to learn.

Responsibilities

You will work on a small team designing CPU-based subsystems for high performance, low power wireless SoCs. This role involves defining debug features, collaborating with designers, and guiding validation engineers to diagnose issues.