JOB DESCRIPTION

The NPU IP team is looking for a Digital Verification Engineer to work on validation of NPUs AI accelerator products. In this role you will join the Hardware Validation team working closely with verification engineers, Hardware Engineers and AI architects to validate the architecture blocks within the NPU IP portfolio.

Your responsibilities will include:

• Functional Validation of Computer Vision and Deep Learning AI accelerators blocks.
• Develop testbench and validation methodology of complex digital design block(s).
• Implementation of functional verification environments (Testbench, Coverage, Assertions).
• Development of test plans and test cases.
• Implementation of checkers, random test generators, high level transactional models and bus functional models (BFMs).

Preferred Knowledge:

• Knowledge in UVM validation and Formal validation techniques.
• Knowledge in Processor-Based, RTEMs and Embedded C Validation.
• Knowledge with programming languages such as SystemC, C++, Perl, TCL, Shell scripting, Python, System-Verilog.
• Knowledge of SoC based CPUs, NoCs, AMBA Protocols, Memory controllers.
• Knowledge on Low Power Verification techniques.

Leixlip is the primary location for this position, however, we offer flexibility to support your work/life balance arrangements.

QUALIFICATIONS

Graduate in Computer Science, Computer/Electronic Engineering or a similar field;

• Background in the pre-silicon verification of ASIC, SoC or FPGA designs.
• A self-starter with the ability to assume leadership roles.
• Ability to work well in a diverse team environment.
• Experience with industry standard development and verification tools and methodologies.

• Functional Validation of Computer Vision and Deep Learning AI accelerators blocks.
• Develop testbench and validation methodology of complex digital design block(s).
• Implementation of functional verification environments (Testbench, Coverage, Assertions).
• Development of test plans and test cases.
• Implementation of checkers, random test generators, high level transactional models and bus functional models (BFMs)