Design Engineer I at Silicon Labs

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

20 Sep, 26

Salary

146250.0

Posted On

22 Jun, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, SDC Constraints, Digital IC Design, RTL to GDSII, Physical Design, Timing Closure, Signoff Methodologies, Python, Perl, Tcl, Linux/Unix, EDA Tools, Low-Power Design, Cadence Tempus, Synopsys PrimeTime, Digital Implementation

Industry

Semiconductor Manufacturing

Description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com. Meet the Team You’ll join the Physical Implementation Team. This team is responsible for transforming RTL designs into manufacturable silicon, driving the implementation flow from synthesis through physical design and final tapeout (GDSII). Our team works closely with Design, Verification, DFT, and Technology teams to ensure high-performance, low-power, and reliable integrated circuits are delivered on schedule. This is a great opportunity for engineers who are passionate about digital design, timing analysis, and seeing their work become real silicon. Responsibilities Support the physical implementation of digital designs from RTL through GDSII/tapeout. Develop and maintain timing constraints (SDC) for block-level and chip-level designs. Perform static timing analysis (STA) to identify and resolve timing violations across multiple operating conditions. Assist with block-level and chip-level signoff activities, ensuring designs meet performance, power, and quality targets. Collaborate with cross-functional teams including Design Engineering, Verification, DFT, and CAD to drive implementation closure. Analyze timing reports and recommend design or constraint improvements. Participate in debugging and resolving implementation, timing, and design integration issues. Contribute to the continuous improvement of physical implementation methodologies, flows, and automation. Skills You Need Minimum Qualifications Master's degree in Electrical Engineering, Computer Engineering, or a related field. Academic or project experience with Static Timing Analysis (STA). Experience developing or working with timing constraints (SDC). Understanding of digital IC design and implementation concepts. Knowledge of chip-level or block-level signoff methodologies. Strong analytical and problem-solving skills. Effective communication skills and ability to work in a collaborative team environment. The following qualifications will be considered a plus: Experience with industry-standard STA tools such as Cadence Tempus or Synopsys PrimeTime. Coursework, research, or project experience in digital implementation, physical design, or timing closure. Programming or scripting experience with Python, Perl, or Tcl. Familiarity with semiconductor design flows from RTL through tapeout. Exposure to low-power design techniques and timing optimization methodologies. Experience working with Linux/Unix environments and EDA tool flows. Benefits & Perks You can look forward to the following benefits: Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans Highly competitive salary 401k plan with match and Roth plan option Equity rewards (RSUs) Life/AD&D and disability coverage Flexible spending accounts Adoption assistance Back-Up childcare Additional benefit options (Commuter benefits, Legal benefits, Pet insurance) Flexible PTO schedule 3 paid volunteer days per year Tuition reimbursement Free downtown parking Onsite gym Monthly wellness offerings Free snacks Monthly company updates with our CEO #LI-MA1 #LI-Hybrid The annualized base pay range for this role is expected to be between $78,750 - $146,250 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant’s skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package. Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law. At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way. Please note that our Company never asks for personal information unrelated to the job application process, such as bank or credit card data and never charges any fees to apply to any jobs. For more information please click here.

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Responsibilities

Support the physical implementation of digital designs from RTL through tapeout, focusing on timing constraints and static timing analysis. Collaborate with cross-functional teams to resolve timing violations and improve implementation methodologies.